MSC7119 datasheet(42/56 Pages) FREESCALE

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MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6

Hardware Design Considerations

Freescale Semiconductor

3.2

Power Supply Design Considerations

This section outlines the MSC7119 power considerations: power supply, power sequencing, power planes, decoupling, power

supply filtering, and power consumption. It also presents a recommended power supply design and options for low-power

consumption. For information on AC/DC electrical specifications and thermal characteristics, refer to Section 2.

•

Power Supply. The MSC7119 requires four input voltages, as shown in Table 32.

You should supply the MSC7119 core voltage via a variable switching supply or regulator to allow for compatibility

with possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%)

across VDDC and GND and the I/O section is supplied with 3.3 V (± 10%) across VDDIO and GND. The memory and

reference voltages supply the DDR memory controller block. The memory voltage is supplied with 2.5 V across VDDM

and GND. The reference voltage is supplied across VREF and GND and must be between 0.49 × VDDM and 0.51 ×

VDDM. Refer to the JEDEC standard JESD8 (Stub Series Terminated Logic for 2.5 Volts (STTL_2)) for memory

voltage supply requirements.

•

Power sequencing. One consequence of multiple power supplies is that the voltage rails ramp up at different rates when

power is initially applied. The rates depend on the power supply, the type of load on each power supply, and the way

different voltages are derived. It is extremely important to observe the power up and power down sequences at the

board level to avoid latch-up, forward biasing of ESD devices, and excessive currents, which all lead to severe device

damage. The correct power-up sequence is as follows:

— Turn on the highest supply first (3.3 V).

— Turn on the 2.5 V supply.

— Turn on the lowest supply last (1.2 V).

The correct power-down sequence is as follows:

— Turn off the lowest supply first (1.2 V).

— Turn off the 2.5 V supply.

— Turn off the highest supply last (3.3 V).

At any instant during power-up and power-down, the 2.5 V supply must maintain a differential of +0.7 V or more

below the 3.3 V supply. Also, at any instant, the 1.2 V supply must maintain a differential of +0.7 V or more below the

2.5 V supply, as shown in Figure 30. The power-down sequence is not as critical as the power-up sequence.

Table 32. MSC7119 Voltages

Voltage

Symbol

Value

Core

VDDC

1.2 V

Memory

VDDM

2.5 V

Reference

VREF

1.25 V

I/O

VDDIO

3.3 V

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