TDA8366H datasheet(14/48 Pages) PHILIPS

14 / 48 page

January 1995

Philips Semiconductors

Objective speciﬁcation

I2C-bus controlled PAL/NTSC TV

processor

TDA8366

Table 12 Vertical divider mode

Table 13 Video ident mode

Table 14 Long blanking mode

Table 15 EHT tracking mode

Table 16 Enable vertical guard (RGB blanking)

Table 17 Service blanking

Table 18 Overvoltage input mode

Table 19 Vertical deﬂection mode

NCIN

VERTICAL DIVIDER MODE

normal operation

switched to search window

VID

VIDEO IDENT MODE

ϕ1 loop switched on and off

not active

LBM

BLANKING MODE

adapted to standard (50 or 60 Hz)

ﬁxed in accordance with 50 Hz standard

HCO

TRACKING MODE

EHT tracking only on vertical

EHT tracking on vertical and EW

EVG

VERTICAL GUARD MODE

not active

active

SBL

SERVICE BLANKING MODE

0off

1on

PRD

OVERVOLTAGE MODE

detection mode

protection mode

EXP

VERTICAL DEFLECTION MODE

normal

compress

expand

expand and lift

Table 20 Horizontal frequency during switch-on

Table 21 Condition Y/C input

Table 22 PAL/NTSC matrix

Table 23 Colour crystal PLL

Table 24 Y-delay adjustment; note 1

Note

1. For an equal delay of the luminance and chrominance

signal the delay must be set at a value of 160 ns. This

is only valid for a CVBS signal without group

delay distortions.

Table 25 RGB blanking

Table 26 Noise coring (peaking)

SFM

START-UP FREQUENCY

maximum

nominal

CVS

Y-INPUT MODE

switched to Y/C mode

switched to CVBS mode

MAT

MATRIX

adapted to standard

1PAL

PHL

STATE

PLL closed

oscillator free-running

YD0 to YD3

Y-DELAY

YD3

∗ 160 ns +

YD2

∗ 80 ns +

YD1

∗ 40 ns +

YD0

∗ 40 ns

RBL

RGB BLANKING

not active

active

COR

NOISE CORING

0off

1on

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