AP72202

Document number: DS46304 Rev. 1 - 2

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May 2024

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AP72202

Application Information (continued)

Writing to a Sequential Register

Figure 8 below shows the protocol for writing to sequential registers. This protocol is similar to the write byte protocol, except the master continues

to write additional data after is receives an ACK from the slave that it successfully received the previous data byte.

The slave’s register pointer will

auto-increment by one after each byte received. When the master is done writing, it issues a STOP or REPEATED START. The writing to sequential

registers protocol is as follows:

1.

The master sends a START condition.

2.

The master sends the 7-bit slave address followed by a write bit (R/nW = 0).

3.

The addressed slave sends an ACK bit by pulling SDA low.

4.

The master sends an 8-bit register pointer.

5.

The slave acknowledges the register pointer.

6.

The master sends a data byte.

7.

The slave acknowledges the data byte.

8.

The next falling edge on SCL loads the data byte into its target register and the data becomes active.

9.

Steps 6 to 8 are repeated as many times as the master requires.

10. The master sends a STOP condition or a REPEATED START condition.

Figure 8. Writing to Sequential Registers X to N

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