AP72202

Document number: DS46304 Rev. 1 - 2

2 of 30

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May 2024

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AP72202

Typical Applications Circuit

Pin Descriptions

Pin

Name

Pin Number

Function

20 BALLS

VIN

A1

Input supply for the logic control circuitries.

OCP

A2

OCP program the current limit. LOW will set the OCP threshold to 2A. HIGH will set the OCP threshold to 4.3A.

I2C can override the MODE pin. See the register for more detail.

MODE

A3

MODE logic input. LOW for PFM operation. HIGH for forced PWM. There is an internal 5.5M

Ω resistor from MODE

and GND to set the IC in PFM if left floating. I2C can override the MODE pin. See the register for more detail.

SDA

A4

I2C Data I/O.

SCL

A5

I2C Clock Input.

FB

B1

Feedback Input. FB senses the output voltage and regulates it. Connect FB to VOUT.

PG

B2

Open-drain power-good output that is pulled to GND when the output voltage is out of its regulation limits or

during soft-start interval. Active high by default. There is an internal 5M

Ω pullup resistor to VIO.

GND

B3

Analog ground that is used for control.

EN

B4

Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator; low to

turn it off.

VIO

B5

Input supply for the I2C and PG internal pullup resistor.

VOUT

C1, D1

Buck-Boost output.

SW2

C2, D2

Switch Node 2.

PGND

C3, D3

Power Ground.

SW1

C4, D4

Switch Node 1.

PVIN

C5, D5

Power Input. Bypass PVIN to GND with a 10µF capacitor to eliminate noise on the input to the IC.

See Input Capacitor.

PVIN

EN

SCL

SDA

GND

PGND

PG

VOUT

SW2

SW1

L1

1µH

VOUT

C2

2x22µF

C1

10µF

VIN = 2.3V to 5.5V

FB

VIO

OCP

VIN

MODE

Figure 1. Typical Application Circuit