MCP23016

DS20090C-page 24

© 2007 Microchip Technology Inc.

TABLE 2-5:

Param

No.

Symbol

Characteristic

Min

Max

Units

Conditions

100

Clock High Time

100 kHz mode

4.0

—

µs

(Note 1)

400 kHz mode

0.6

—

µs

101

Clock Low Time

100 kHz mode

4.7

—

µs

(Note 1)

400 kHz mode

1.3

—

µs

102

SDA and SCL Rise

Time

100 kHz mode

—

1000

ns

(Note 1)

400 kHz mode

300

ns

10 - 400 pF

103

SDA and SCL Fall

Time

100 kHz mode

—

300

ns

(Note 1)

400 kHz mode

300

ns

10 - 400 pF

90

START Condition

Setup Time

100 kHz mode

4.7

—

µs

Only relevant for repeated

START condition (Note 1)

400 kHz mode

0.6

—

µs

91

START Condition

Hold Time

100 kHz mode

4.0

—

µs

After this period, the first

clock pulse is generated

(Note 1)

400 kHz mode

0.6

—

µs

106

Data Input Hold

Time

100 kHz mode

0

—

ns

(Note 1)

400 kHz mode

0

0.9

µs

107

Data Input Setup

Time

100 kHz mode

250

—

ns

(Note 1) (Note 3)

400 kHz mode

100

—

ns

92

STOP Condition

Setup Time

100 kHz mode

4.7

—

µs

(Note 1)

400 kHz mode

0.6

—

µs

109

Output Valid from

Clock

100 kHz mode

—

3500

ns

(Note 1) (Note 2)

400 kHz mode

—

—

ns

110

Bus Free Time

100 kHz mode

4.7

—

µs

Time the bus must be free

before a new transmis-

sion can start (Note 1)

400 kHz mode

1.3

—

µs

Bus Capacitive Loading

—

400

pF

111

Clock wait time

after ninth pulse

100 kHz mode

12 µs

—

µs

Time the bus must remain

free after the ninth clock

pulse before a new

transmission can start.

400 kHz mode

12 µs

—

µs

Note 1:

These parameters are characterized but not tested.

2:

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3:

≥ 250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,