2000 Mar 16

31

Philips Semiconductors

Preliminary specification

5 V mixers/oscillators and synthesizers for

cable TV and VCR 2-band tuners

TDA6502; TDA6502A;

TDA6503; TDA6503A

13.5.2

Tables 25 and 26 show the various read sequences where:

S = START bit

A = acknowledge bit

XX = read status byte

X = no acknowledge from the master means end of sequence

P = STOP bit

Table 25 One status byte acquisition

Table 26 Two status bytes acquisition

13.6

Examples of 3-wire bus data format sequences for TDA6502 and TDA6503

13.6.1

Conditions:

Port register PUHF is ‘on’.

Table 27 18-bit sequence

The reference divider is automatically set to 64 assuming that bit RSB has been set to logic 1 at power-on. If bit RSB has

been set to logic 0, in a previous 27-bit sequence, the reference divider will still be set at 80. In this event, the 18-bit

sequence has to be adapted to the 80 divider ratio.

13.6.2

Conditions:

Port register PUHF is ‘on’.

Table 28 19-bit sequence

The reference divider is automatically set to 128 assuming that bit RSB has been set to logic 1 at power-on. If bit RSB

has been set to logic 0 in a previous 27-bit sequence, the reference divider will still be set at 80. In this event, the 19-bit

sequence has to be adapted to the 80 divider ratio.

START

ADDRESS BYTE

ACK

STATUS BYTE

ACK

STOP

SC3

A

XX

X

P

START

ADDRESS BYTE

ACK

STATUS BYTE

ACK

STATUS BYTE

ACK

STOP

S

C3

A

XX

A

XX

X

P

PUHF FMST PVHFH PVHFL

N13

N12

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

N0

1

0

0

0

1

1

1

0

0100000000

PUHF FMST PVHFH PVHFL

N14

N13

N12

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

N0

1

0

0

0

10100

0101000000