TDA6402 datasheet(17/40 Pages) PHILIPS

17 / 40 page

2000 Jan 24

Philips Semiconductors

Product speciﬁcation

5 V mixers/oscillators and synthesizers for

cable TV and VCR 2-band tuners

TDA6402; TDA6402A;

TDA6403; TDA6403A

CE/AS INPUT (CHIP ENABLE/ADDRESS SELECTION)

VCE/ASL

LOW-level input voltage

−

1.5

VCE/ASH

HIGH-level input voltage

−

5.5

ICE/ASH

HIGH-level input current

VCE/AS = 5.5 V

−−

µA

ICE/ASL

LOW-level input current

VCE/AS =0V

−10

−−µA

CL AND DA INPUTS

VCL/DAL

LOW-level input voltage

−

1.5

VCL/DAH

HIGH-level input voltage

−

5.5

ICL/DAH

HIGH-level input current

VBUS = 5.5 V; VCC =0V

−−

µA

VBUS = 5.5 V; VCC = 5.5 V

−−

µA

ICL/DAL

LOW-level input current

VBUS = 1.5 V; VCC =0V

−−

µA

VBUS =0V; VCC = 5.5 V

−10

−−µA

DA OUTPUT (I2C-BUS MODE)

IDAH

leakage current

VDA = 5.5 V

−−

µA

VDA

output voltage

IDA = 3 mA (sink current)

−−

0.4

CLOCK FREQUENCY

fclk

clock frequency

−

100

150

kHz

CHARGE PUMP OUTPUT CP

ICPH

HIGH-level input current

(absolute value)

CP = 1

−

280

−µA

ICPL

LOW-level input current

(absolute value)

CP = 0

−

−µA

VCP

output voltage

PLL is locked; Tamb =25 °C

−

1.95

−

ICPleak

off-state leakage current

T2 = 0; T1 = 1

−15

−0.5

+15

TUNING VOLTAGE OUTPUT VT

IVTOFF

leakage current when

switched off

OS = 1; tuning supply = 33 V

−−

µA

VVT

output voltage when the loop

is closed

OS = 0; T2 = 0; T1 = 0; T0 = 1;

RLOAD =22kΩ; tuning supply = 33 V

0.2

−

32.7

3-WIRE BUS TIMING

tHIGH

clock HIGH time

see Fig.7

−−µs

tSU;DA

data set-up time

see Fig.7

−−µs

tHD;DA

data hold time

see Fig.7

−−µs

tSU;ENCL

enable to clock set-up time

see Fig.7

−−µs

tHD;ENDA

enable to data hold time

see Fig.7

−−µs

tEN

enable time between two

transmissions

see Fig.8

−−µs

tHD;ENCL

enable to clock active edge

hold time

see Fig.8

−−µs

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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