TDA6402 datasheet(7/40 Pages) PHILIPS

7 / 40 page

2000 Jan 24

Philips Semiconductors

Product speciﬁcation

5 V mixers/oscillators and synthesizers for

cable TV and VCR 2-band tuners

TDA6402; TDA6402A;

TDA6403; TDA6403A

Fig.2

Pin configuration for TDA6402 and

TDA6402A.

handbook, halfpage

UHFIN1

UHFIN2

VHFIN

RFGND

IFFIL1

IFFIL2

PVHFL

PVHFH

PUHF

FMST

CE/AS

UHFOSCIB2

UHFOSCOC2

UHFOSCOC1

UHFOSCIB1

OSCGND

VHFOSCIB

VHFOSCOC

GND

IFOUT

VCC

XTAL

LOCK/ADC

TDA6402

TDA6402A

MGE690

Fig.3

Pin configuration for TDA6403 and

TDA6403A.

handbook, halfpage

UHFIN1

UHFIN2

VHFIN

RFGND

IFFIL1

IFFIL2

PVHFL

PVHFH

PUHF

FMST

CE/AS

UHFOSCIB2

UHFOSCOC2

UHFOSCOC1

UHFOSCIB1

OSCGND

VHFOSCIB

VHFOSCOC

GND

IFOUT

VCC

XTAL

LOCK/ADC

TDA6403

TDA6403A

MGE691

PLL FUNCTIONAL DESCRIPTION

The device is controlled via the I2C-bus or the 3-wire bus,

depending on the voltage applied on the SW input.

A HIGH-level on the SW input enables the 3-wire bus;

CE/AS, DA and CL inputs are used as enable (CE), data

and clock inputs respectively. A LOW-level on SW input

enables the I2C-bus; the CE/AS, DA and CL inputs are

used as address selection (AS), SDA and SCL input

respectively (see Table 2).

Table 2

Bus mode selection

SYMBOL

3-WIRE BUS MODE

I2C-BUS MODE

TDA6402;

TDA6402A

TDA6403;

TDA6403A

HIGH-level or OPEN

LOW-level or GND

CE/AS

enable input

address selection input

data input

serial data input

clock input

serial clock input

LOCK/ADC

LOCK/TEST output

ADC input/TEST output

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