ADIN2111BCPZ-R7 datasheet(68/129 Pages) AD

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Data Sheet

ADIN2111

REGISTERS

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Rev. A | 68 of 129

Table 70. Bit Descriptions for SCRATCHn

Bits

Bit Name

Description

Reset

Access

[31:0]

SCRATCH_DATA

Scratch Data.

0x0

R/W

MAC Reset Status Register

Address: 0x3B, Reset: 0x00000003, Name: MAC_RST_STATUS

If this register returns 0x00000000_00000001 when read, the oscillator clock is active but the 25 MHz crystal clock is not active.

If this register returns 0x00000000_00000003 when read, both the oscillator clock and the 25 MHz crystal clock are active.

If this register returns 0x00000000_00000000 (SDO output pad is enabled as CS is low), the SPI slave and MAC core are both still in reset.

Only single SPI reads of this register are supported. An SPI burst read must not increment into this register.

Table 71. Bit Descriptions for MAC_RST_STATUS

Bits

Bit Name

Description

Reset

Access

[31:2]

RESERVED

Reserved.

0x0

MAC_CRYSL_CLK_RDY

MAC Crystal Clock Ready. If 0, this field indicates that the MAC core has released from reset.

If 1, this field indicates that the MAC core released from reset. The MAC core is released from

reset when the crystal clock (25 MHz) is ready.

0x1

MAC_OSC_CLK_RDY

MAC Oscillator Clock Ready.

0x1

Software Reset Register

Address: 0x3C, Reset: 0x00000000, Name: SOFT_RST

Table 72. Bit Descriptions for SOFT_RST

Bits

Bit Name

Description

Reset

Access

[31:16]

RESERVED

Reserved.

0x0

[15:0]

RST_KEY

Software Reset. Write a pair of keys in order and back to back on the SPI to trigger a reset.

0x0

0x4F1C: Key 1 to reset the MAC logic only.

0xC1F4: Key 2 to reset the MAC logic only. Reset does not take effect until CS is brought high and CS must

be held asserted for at least 100 ns for the reset to take effect. If the MACPHY is in software power-down, the

MAC_ONLY reset has no effect. That is, CRSM_SFT_P_CNTRL.CRSM_SFT_PD must be 0.

0x6F1A: Key 1 to request release of reset to the MAC core logic. Use MAC_RST_EXIT_REQ_KEYx to request

a release of reset to the MAC core logic when the 25 MHz crystal clock is not available. This brings the MAC out

of reset using the oscillator clock (12.5 MHz to 25.7 MHz). SPI accesses can then proceed at 15 MHz to allow

debug access to MAC and PHY registers.

0xA1F6: Key 2 to request release of reset to the MAC core logic.

Inject an Error on MISO from the DUT Register

Address: 0x3D, Reset: 0x00000000, Name: SPI_INJ_ERR

Table 73. Bit Descriptions for SPI_INJ_ERR

Bits

Bit Name

Description

Reset

Access

[31:1]

RESERVED

Reserved.

0x0

TEST_SPI_INJ_ERR

Inject an Error on the SPI MISO Path. This function allows software to test that errors received on

MISO are properly detected in software.

0x0

R/W

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