ADIN1300BCPZ-R7 datasheet(2/96 Pages) AD

2 / 96 page

Data Sheet

ADIN1300

TABLE OF CONTENTS

analog.com

Rev. B | 2 of 96

Features................................................................ 1

Applications........................................................... 1

General Description...............................................1

Functional Block Diagram......................................5

Specifications........................................................ 6

Timing Characteristics........................................8

Absolute Maximum Ratings.................................13

Thermal Resistance......................................... 13

ESD Caution.....................................................13

Pin Configuration and Function Descriptions...... 14

Typical Performance Characteristics................... 17

Theory of Operation.............................................19

Overview.......................................................... 19

Analog Front End (AFE) .................................. 19

MAC Interface.................................................. 20

Autonegotiation................................................ 21

Autonegotiation Disabled................................. 21

Management Interface..................................... 22

MDI Interface....................................................23

Reset Operation............................................... 23

Power-Down Modes......................................... 26

Status LED....................................................... 27

Link Status, LINK_ST....................................... 28

PHY Output Clocks.......................................... 28

Power Supply Domains.................................... 28

Hardware Configuration Pins...............................29

Hardware Configuration Pin Functions.............29

On-Chip Diagnostics............................................35

Loopback Modes..............................................35

Frame Generator and Checker........................ 36

Cable Diagnostics............................................ 37

Enhanced Link Detection................................. 37

Start of Packet Indication................................. 38

Typical Power Consumption................................ 39

Power Supplies................................................ 39

Applications Information...................................... 41

System Overview............................................. 41

Low Power Termination in 100BASE-TX..........42

Repeater or Back to Back Mode...................... 42

RGMII Timing Examples.................................. 43

Component Recommendations........................44

Power Requirements........................................45

Supply Decoupling........................................... 46

PHY Core Register Summary.......................... 47

PHY Core Register Details...............................49

Subsystem Register Summary.........................85

Subsystem Register Details ............................ 86

PCB Layout Recommendations.......................... 94

PHY Package Layout....................................... 94

Component Placement.....................................94

MDI, Differential Pair Routing...........................94

MAC Interface Pins.......................................... 94

Power and Ground Planes............................... 95

Outline Dimensions............................................. 96

Ordering Guide.................................................96

Evaluation Boards............................................ 96

REVISION HISTORY

5/2024—Rev. A to Rev. B

Changes to Features Section.......................................................................................................................... 1

Change to Note 3, Table 1............................................................................................................................... 6

Changes to Table 14......................................................................................................................................16

Change to Link Status, LINK_ST Section...................................................................................................... 28

Changes to Hardware Configuration Pins Section.........................................................................................29

Added Note 3, Table 23................................................................................................................................. 30

Changes to Figure 31 and Figure 32............................................................................................................. 41

Changes to RGMII Timing Examples Section................................................................................................43

Changes to External Clock Input Section...................................................................................................... 44

Changes to Table 51......................................................................................................................................60

Change to Frame Checker Count High Register Section.............................................................................. 72

Changes to Crystal Placement and Routing Section..................................................................................... 94

8/2022—Rev. 0 to Rev. A

Changes to Features Section.......................................................................................................................... 1

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