REV. B

AD807

–10–

AD807

DATAOUTN

DATAOUTP

VCC2

CLKOUTN

CF1

CF2

VEE

SDOUT

PIN

NIN

AVCC1

THRADJ

AVEE

SDOUT

TP7

R14

50

R15

50

VCC1

CLKOUTP

AVCC2

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

TP5

TP1

TP2

CD

R5 100

R6 100

R10

154

R9

154

C7

R7 100

R8 100

C8

R12

154

R11

154

TP4

R2

100

R1

100

C2 0.1 F

C3 0.1 F

C4 0.1 F

C5 0.1 F

R4

100

R3

100

C2

0.1 F

DATAOUTN

DATAOUTP

CLKOUTN

CLKOUTP

NOTES:

1. ALL CAPACITORS ARE CHIP,

15pF ARE MICA.

2. 150nH ARE SMT

3. C7, C8, C10, C11 ARE 0.1 F

BYPASS CAPACITORS

C1 0.1 F

J1

J2

J3

J4

TP6

R13

THRADJ

C10

C11

C15

0.1 F

C14

0.1 F

R16

301

C12

2.2 F

R17

3.65k

C13

0.1 F

NC

IIN

NC

VBYP

+VS

+OUT

–VS

–OUT

AD8015

1

2

3

4

8

7

6

5

ABB HAFO 1A227

FC HOUSING

0.8A/W, 0.7pF

2.5GHz

0.01 F

0.1 F

NC = NO CONNECT

0.1 F

10 F

15pF

150nH

150nH

15pF

TP3

5V

C9

10 F

50

LINE

50

LINE

Figure 14. Low Cost 155 Mbps Fiber Optic Receiver Schematic

Table I. AD807—AD8015 Fiber Optic Receiver Circuit:

Output Bit Error Rate and Output Jitter vs. Input Power

Average Optical

Input Power

Output Bit

Output Jitter

(dBm)

Error Rate

(ps rms)

–6.4

Loses Lock

–6.5

7.5

× 10–3

–6.6

9.4

× 10–4

–6.7

0

× 10–14

–7.0 to –35.5

0

× 10–14

<40

–36.0

3

× 10–12

<40

–36.5

4.8

× 10–10

–37.0

2.8

× 10–8

–38.0

1.3

× 10–5

–39.0

1.0

× 10–3

–39.2

1.9

× 10–3

–39.3

Loses Lock

APPLICATIONS

Low Cost 155 Mbps Fiber Optic Receiver

The AD807 and AD8015 can be used together for a complete

155 Mbps Fiber Optic Receiver (Quantizer and Clock Recovery,

and Transimpedance Amplifier) as shown in Figure 14.

The PIN diode front end is connected to a single mode 1300 nm

laser source. The PIN diode has 3.3 V reverse bias, 0.8 A/W

responsively, 0.7 pF capacitance, and 2.5 GHz bandwidth.

The AD8015 outputs (POUT and NOUT) drive a differential,

constant impedance (50

Ω) low-pass filter with a 3 dB cutoff

of 100 MHz. The outputs of the low-pass filter are ac coupled

to the AD807 inputs (PIN and NIN). The AD807 PLL damp-

ing factor is set at 7 using a 0.22

µF capacitor.

503mV

100mV/

DIV

–497mV

48.12ns

1ns/DIV

58.12ns

Figure 15. Receiver Output (Data) Eye Diagram,

–7.0 dBm Optical Input

503mV

100mV/

DIV

–497mV

49.12ns

1ns/DIV

59.12ns

Figure 16. Receiver Output (Data) Eye Diagram,

–36.0 dBm Optical Input