REV. B

AD807

–5–

Bandwidth

This describes the frequency at which the AD807 attenuates

sinusoidal input jitter by 3 dB.

Peaking

This describes the maximum jitter gain of the AD807 in dB.

Damping Factor,

ζ

Damping factor,

ζ describes the compensation of the second

order PLL. A larger value of

ζ corresponds to more damping

and less peaking in the jitter transfer function.

Acquisition Time

This is the transient time, measured in bit periods, required for

the AD807 to lock onto input data from its free-running state.

Symmetry—Recovered Clock Duty Cycle

Symmetry is calculated as (100

× on time)/period, where on

time equals the time that the clock signal is greater than the

midpoint between its “0” level and its “1” level.

Bit Error Rate vs. Signal-to-Noise Ratio

AD807 Bit Error Rate vs. Signal-to-Noise Ratio performance is

shown in TPC 6. Wideband amplitude noise is summed with

the input data signal as shown in Figure 4. Performance is

shown for input data levels of 5 mV and 10 mV.

VCM

2mV p-p

SCOPE

PROBE

AD807 QUANTIZER

EPITAXX ERM504

VCM

BINARY

OUTPUT

a. Single-Ended Input Application

VCM

1mV p-p

SCOPE

PROBE

AD807 QUANTIZER

AD8015

DIFFERENTIAL

OUTPUT TIA

VCM

BINARY

OUTPUT

+OUT

–OUT

b. Differential Input Application

Figure 3. (a–b) Single-Ended and Differential Input

Applications

+

+

50

50

0.47 F

0.47 F

75

1.0 F

100

GND

5V

+

–

POWER

COMBINER

POWER

COMBINER

PIN

NIN

DIFFERENTIAL

SIGNAL

SOURCE

POWER

SPLITTER

NOISE

SOURCE

FILTER

100MHz

D.U.T.

AD807

Figure 4. Bit Error Rate vs. Signal-to-Noise Ratio

Test: Block Diagram

VBE 0.8V

AVCC2

DIFFERENTIAL

INPUT

CURRENT SOURCES

HEADROOM

0.7V

0.5mA

1mA

0.5mA

AVEE

400

400

a. Quantizer Differential Input Stage

5.9k

1.2V +VBE

AVEE

THRADJ

94.6k

b. Threshold Adjust

150

VEE

SDOUT

150

VCC1

IOH

IOL

c. Signal Detect Output (SDOUT)

450

450

VCC2

DIFFERENTIAL

INPUT

2.5mA

VEE

d. PLL Differential Output Stage—DATAOUT(N),

CLKOUT(N)

Figure 5. (a–d) Simplified Schematics