PI0512WS Page 6 of 8 – July 26, 2001

Clock and Voltage Requirements

Clocks requirements are relatively simple. As it was indicated in Figure 5 and Table 1, there

are only three input signals that require clocked inputs. They are CLK, the clock for the shift

register, START, the shift register start pulse, and RESET, the reset control gate. However, in

certain applications where the internal reset circuitry is unused, RESET can be tied to ground.

Figure 6. Timing diagram.

Table 2 . Symbol definitions and timing specifications for timing diagram.

Item

Symbol

Min

Typical

Max

Units

Clock cycle time

to

5

µs

Clock pulse width

tw

1

µs

Clock duty cycle

20

50

80

%

Prohibit crossing time of Start Pulse

tprh

0

ns

Data setup time

tds

50

ns

Data hold time

tdh

100

ns

End Of Scan delay

tdeo

300

ns

End Of Scan off

tdee

300

ns

Signal delay time

tsd

50

ns

Signal settling time

tsh

500

ns

The timing specifications and the symbol definition for Figure 6 are listed in Table 2. The

control clock amplitudes for I/Os are compatible with the 5-Volt CMOS devices.