Table 15. AC characteristics

Symbol

Alt.

Parameter

Standard mode Fast-mode Fast-mode plus

Unit

Min.

Max.

Min. Max.

Min.

Max.

fC

fSCL

Clock frequency

-

100

-

400

-

1000

kHz

tCHCL

tHIGH Clock pulse width high

4

-

600

-

260

-

ns

tCLCH

tLOW

Clock pulse width low

4.7

-

1300

-

500

-

ns

tQL1QL2(1)

tF

SDA (out) fall time

-

300

20(2)

300

20(2)

120

ns

tXH1XH2

tR

Input signal rise time

-

1000

(3)

(3)

(4)

(4)

ns

tXL1XL2

tF

Input signal fall time

-

300

(3)

(3)

(4)

(4)

ns

tDVCH

tSU:DAT Data in set up time

250

-

100

-

50

-

ns

tCLDX

tHD:DAT Data in hold time

0

-

0

-

0

-

ns

tCLQX (5)

tDH

Data out hold time

100

-

100

-

100

-

ns

tCLQV (6)

tAA

Clock low to next data valid (access time)

-

4500

-

900

-

450

ns

tCHDL

tSU:STA Start condition setup time

4700

-

600

-

250

-

ns

tDLCL

tHD:STA Start condition hold time

4000

-

600

-

250

-

ns

tCHDH

tSU:STO Stop condition set up time

4000

-

600

-

250

-

ns

tDHDL

tBUF

Time between Stop condition and next Start

condition

4700

-

1300

-

500

-

ns

tWLDL(1)(7) tSU:WC WC set up time (before the Start condition)

0

-

0

-

0

-

µs

tDHWH (1)(8) tHD:WC WC hold time (after the Stop condition)

1

-

1

-

1

-

µs

tW

tWR

Write time

-

5

-

5

-

5

ms

tNS

-

Pulse width ignored (input filter on SCL and

SDA) - single glitch

-

50

-

50

-

50

ns

tWU(1)(9)

-

Wake up time

-

5

-

5

-

5

μs

1. Evaluated by characterization – Not tested in production.

2. With CL = 10 pF.

3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification

that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz

4. There are no minimum or maximum values for the input signal rise and fall times. However, it is recommended by the I²C

specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when fC < 1 MHz.

5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of

SDA.

6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming

that Rbus × Cbus time constant is within the values specified in Figure 17 and Figure 18.

7. WC=0 set up time condition to enable the execution of a write command.

8. WC=0 hold time condition to enable the execution of a write command.

9. Wake up time: Delay between the VCCmin stable and the first accepted commands.

M24256E-F

DS12687 - Rev 3

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