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RT7204E датащи(PDF) 39 Page - Richtek Technology Corporation |
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RT7204E датащи(HTML) 39 Page - Richtek Technology Corporation |
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39 / 45 page ![]() F RT7204E Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. RT7204E_DS-00 May 2024 www.richtek.com 39 16.9 VIN Detection and LPS Protection The RT7204E can detect the input voltage and implement LPS protection by sensing the drain voltage of the low- side SR MOSFET, as shown in Figure 6. The recommended divider resistance, RVTR_H, between the SR MOSFET drain terminal and the VTR pin is 150k . Due to varying component stress and thermal considerations under AC high/low line conditions, the power rating and OTP threshold can be adaptively customized through input voltage detection for a more compact design. The VTR pin also provides AC OFF detection to prevent the RT7204E from being reverse biased through the body diode of a blocking N-MOSFET. If there is no switching signal on the VTR within the programmable delay time, a flag will be sent to the MCU to fulfill power saving requirements. 16.10 Thermal Considerations The junction temperature should never exceed the absolute maximum junction temperature TJ(MAX), listed under Absolute Maximum Ratings, to avoid permanent damage to the device. The maximum allowable power dissipation depends on the thermal resistance of the IC package, the PCB layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. The maximum power dissipation can be calculated using the following formula: PD(MAX) = (TJ(MAX) - TA) / JA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and JA is the junction-to- ambient thermal resistance. For continuous operation, the maximum operating junction temperature indicated under Recommended Operating Conditions is 125°C. The junction-to-ambient thermal resistance, JA, is highly package dependent. For a WQFN- 24L 4x4 package, the thermal resistance, JA, is 39.6°C/W on a standard JEDEC low effective-thermal-conductivity two-layer test board. The maximum power dissipation at TA = 25°C can be calculated as below: PD(MAX) = (125°C - 25°C) / (39.6°C/W) = 2.52W for a WQFN-24L 4x4 package. The maximum power dissipation depends on the operating ambient temperature for the fixed TJ(MAX) and the thermal resistance, JA. The derating curve in Figure 16 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Figure 16. Derating Curve of Maximum Power Dissipation 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 25 50 75 100 125 Ambient Temperature (°C) Two-Layer PCB Note 8 . The information provided in this section is for reference only. The customer is solely responsible for the designing, validating, and testing your product incorporating Richtek’s product and ensure such product meets applicable standards and any safety, security, or other requirements. |
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