7.4 Layout

7.4.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp.

Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the

analog circuitry.

• Connect low-ESR, 0.1μF ceramic bypass capacitors between each supply pin and ground, placed as close

to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply

applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Physically separate digital and analog

grounds paying attention to the flow of the ground current.

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

not possible, cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.

• Place the external components as close to the device as possible. Section 7.4.2 shows how keeping RF and

RG close to the inverting input minimizes parasitic capacitance.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

7.4.2 Layout Example

Figure 7-9. Noninverting Layout Example

www.ti.com

LPV521

SNOSB14E – AUGUST 2009 – REVISED JULY 2024

Copyright © 2024 Texas Instruments Incorporated

Submit Document Feedback

25

Product Folder Links: LPV521