LT1010CDD datasheet(7/20 Pages) LINER

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LT1010

1010fc

APPLICATIO S I FOR ATIO

General

These notes briefly describe the LT1010 and how it is

used; a detailed explanation is given elsewhere1. Empha-

sis here will be on practical suggestions that have resulted

from working extensively with the part over a wide range

of conditions. A number of applications are also outlined

that demonstrate the usefulness of the buffer beyond that

of driving a heavy load.

Design Concept

The schematic below describes the basic elements of the

buffer design. The op amp drives the output sink transis-

tor, Q3, such that the collector current of the output

follower, Q2, never drops below the quiescent value (de-

termined by I1 and the area ratio of D1 and D2). As a result,

the high frequency response is essentially that of a simple

follower even when Q3 is supplying the load current. The

internal feedback loop is isolated from the effects of

capacitive loading by a small resistor in the output lead.

INPUT

OUTPUT

V+

V–

1010 AI01

BIAS

idealized buffer with the unloaded gain specified for the

LT1010. Otherwise, it has zero offset voltage, bias current

and output resistance. Its output also saturates to the

internal supply terminals2.

1R. J. Widlar, “Unique IC Buffer Enhances Op Amp Designs; Tames Fast Amplifiers,”

Linear Technology Corp. TP-1, April, 1984.

2See electrical characteristics section for guaranteed limits.

The scheme is not perfect in that the rate of rise of sink

current is noticeably less than for source current. This can

be mitigated by connecting a resistor between the bias

terminal and V +, raising quiescent current. A feature of the

final design is that the output resistance is largely indepen-

dent of the follower quiescent current or the output load

current. The output will also swing to the negative rail,

which is particularly useful with single supply operation.

Equivalent Circuit

Below 1MHz, the LT1010 is quite accurately represented

by the equivalent circuit shown here for both small- and

large-signal operation. The internal element, A1, is an

ROUT

′

′= RSAT – ROUT

VSOS

V+

V–

OUTPUT

INPUT

VOS

VSOS

–

1010 AI02

Loaded voltage gain can be determined from the unloaded

gain, AV, the output resistance, ROUT, and the load resis-

tance, RL, using:

OUT

Maximum positive output swing is given by:

OUT

SOS

SAT

(–

)

The input swing required for this output is:

OUT

⎛

⎝⎜

⎞

⎠⎟

+ ∆

1–

where

∆VOS is the 100mV clipping specified for the

saturation measurements. Negative output swing and

input drive requirements are similarly determined.

Supply Bypass

The buffer is no more sensitive to supply bypassing than

slower op amps as far as stability is concerned. The 0.1

µF

disc ceramic capacitors usually recommended for op

amps are certainly adequate for low frequency work. As

always, keeping the capacitor leads short and using a

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