Philips Semiconductors

Product specification

SC26C94

Quad universal asynchronous receiver/transmitter (QUART)

1995 May 1

25

Commercial/Industrial temperature range. Single numbers apply to both ranges.

NO.

FIGURE

CHARACTERISTIC

LIMITS

UNIT

NO.

FIGURE

CHARACTERISTIC

Min

Typ

Max

UNIT

1

3

D[7:0] Valid after IACKN Low

110/115

ns

2

3

DACKN Low after IACKN Low

10 + 2

90/122 + 3

ns

3

3

D[7:0] floating after IACKN High

0

30

ns

4

3

DACKN High after IACKN High

0

30

ns

5

3

IACKN High after IACKN Low

110/115

ns

NOTE:

1. Consecutive write operations to the upper four bits of the Command Register (CR) require at least three X1/CLK edges; four X1/CLK edges

in the ‘X1/CLK divide by 2 edges’ according to register 2E or 2F setting.

IRQN

IACKN

D[7:0]

DACKN

1

5

2

3

4

SD00165

NOTE: Rise time of IRQN is dependent on external circuit.

Figure 3. Interrupt Knowledge (IACKN) Timing

OSC/N

EVAL/HOLD

IACKN

CIR

VALUE FOR THIS INTERRUPT

SD00166

Figure 4. Interrupt Bid Arbitration Timing