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SST25WF080B датащи(PDF) 15 Page - Microchip Technology

номер детали SST25WF080B
подробное описание детали  8-Mbit, 1.8V, SPI Serial Flash
PDF  44 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

SST25WF080B датащи(HTML) 15 Page - Microchip Technology

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 2013-2022 Microchip Technology Inc. and its subsidiaries
DS20005164H-page 15
SST25WF080B
5.6
Sector Erase
The Sector Erase instruction clears all bits in the
selected 4-Kbyte sector to FFH. A Sector Erase
instruction applied to a protected memory area will be
ignored. Prior to any write operation, the Write Enable
(WREN) instruction must be executed. CE# must remain
active-low for the duration of any command sequence.
The Sector Erase instruction is initiated by executing
an 8-bit command, 20H or D7H, followed by address
bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Sig-
nificant address) are used to determine the sector
address (SAX), remaining address bits can be VIL or VIH.
CE# must be driven high before the instruction is exe-
cuted. Poll the BUSY bit in the Software STATUS reg-
ister, or wait TSE, for the completion of the internal self-
timed Sector Erase cycle. See Figure 5-6 for the Sector
Erase sequence and Figure 6-9 for the flow chart.
FIGURE 5-6:
SECTOR ERASE SEQUENCE
5.7
64-Kbyte Block Erase
The 64-Kbyte Block Erase instruction clears all bits in
the selected 64-Kbyte block to FFH. Applying this
instruction to a protected memory area results in the
instruction being ignored. Prior to any Write operation, the
Write Enable (WREN) instruction must be executed. CE#
must remain active-low for the duration of any com-
mand sequence.
Initiate the 64-byte Block Erase instruction by execut-
ing an 8-bit command, D8H, followed by address bits
[A23-A0]. Address bits [AMS-A16] (AMS = Most Signifi-
cant Address) determine the block address (BAX),
remaining address bits can be VIL or VIH. CE# must be
driven high before executing the instruction. Poll the BUSY
bit in the software status register or wait TBE for the com-
pletion of the internal self-timed Block Erase cycle. See
Figure 5-7 for the 64-Kbyte Block Erase sequences
and Figure 6-9 for the flow chart.
FIGURE 5-7:
64-KBYTE BLOCK ERASE SEQUENCE
CE#
SO
SI
SCK
ADD.
0 1 234 5 6 78
ADD.
ADD.
20 or D7
High-Impedance
15 16
23 24
31
MODE 0
MODE 3
MSb
MSb
CE#
SO
SI
SCK
ADDR
0 1 234 5 6 78
ADDR
ADDR
D8
High-Impedance
15 16
23 24
31
MODE 0
MODE 3
MSb
MSb



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