LAN8804SLASHZMXC1 datasheet(19/91 Pages) MICROCHIP

19 / 91 page

LAN8804

DS00003591G-page 19

Test Mode

TEST_MODE

VIS

For normal operation, this pin must be pulled-down to ground.

No Connect

For normal operation, this pin must be left unconnected.

TABLE 3-6:

JTAG PINS

Name

Symbol

Buffer

Type

Description

JTAG Mux Select

TMS

SRL

JTAG test mode select

JTAG Clock

TCK

SRL

JTAG test clock

JTAG Data Input

TDI

SRL

JTAG data input

JTAG Data

Output

TDO

SRL

JTAG data output

TABLE 3-7:

CONFIGURATION STRAP INPUT PINS

Name

Symbol

Buffer

Type

Description

PHY Base

Address

Configuration

Straps

PHYAD[4:0]

VIS

Configures the PHY Management base address, used with

MDIO bus transactions. The PHY base address,

PHYAD[4:0],

is sampled and latched at power-up/reset and is configurable

to any value from 0 to 1Fh. Each PHY address bit is configured

as follows:

Pulled-up = 1

Pulled-down = 0

The addresses of each of the 4 PHYs are the base value, as

defined by

PHYAD[4:0], plus offsets of 0, 1, 2 and 3. Refer to

Section 3.3.2, "PHY Address (PHYAD[4:0])" for additional

information.

Note:

PHYAD[4:0] must never be greater than ‘h1C.

LED Polarity

Configuration

Straps

PORT0_LED1_POL

PORT0_LED2_POL

PORT1_LED1_POL

PORT1_LED2_POL

PORT2_LED1_POL

PORT2_LED2_POL

PORT3_LED1_POL

PORT3_LED2_POL

VIS

Configures LED polarity as Active High or Active Low. Since

the LED pins are shared with configuration straps, the default

polarity of the LED pins is determined during strap loading.

If the strap value on a pin is a 0, the LED is set as active high

(

PORTx_LEDy_POL=1), since it is assumed that a LED to

ground is used as the pull-down.

Note:

When using a LED as a pull-down strap, an exter-

nal supplemental pull-down resistor may be

needed to ensure a valid low level.

If the strap value on a pin is 1, the LED is set as active low

(

PORTx_LEDy_POL=0), since it is assumed that a LED to

VDDIO is used as the pull-up.

Refer to Section 3.3.5, "LED Polarity

(PORT[3:0]_LED[2:1]_POL)" for additional information.

TABLE 3-5:

MISCELLANEOUS PINS (CONTINUED)

Name

Symbol

Buffer

Type

Description

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