ASC7512 datasheet(8/35 Pages) ETC2

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www.andigilog.com

August 2006 - 70A05003

aSC7512

set, the master must perform a repeat start condition that

indicates to the aSC7512 that a read is about to occur. It is

important to note that if the repeat start condition does not

occur, the aSC7512 will assume that a write is taking place,

and the selected register will be overwritten by the

upcoming data on the data bus. The read sequence is

described in Figure 4. After the start condition, the master

must again send the device address and read/write bit.

This time the R/ W bit must be set to 1 to indicate a read.

The rest of the read cycle is the same as described in the

previous paragraph for reading from a preset pointer

location.

If the pointer is already pointing to the desired register, the

master can read from that register by setting the R/ W bit

(following the slave address) to a 1. After sending an ACK,

the aSC7512 will begin transmitting data during the

following clock cycle. After receiving the 8 data bits, the

master device should respond with a NACK followed by a

stop condition.

If the master is reset while the aSC7512 is in the process of

being read, the master should perform an SMBus reset.

This is done by holding the data or clock low for more than

35ms, allowing all SMBus devices to be reset. This follows

the SMBus 2.0 specification of 25-35ms.

When the aSC7512 detects an SMBus reset, it will prepare

to accept a new start sequence and resume

communication from a known state.

Start

SMBus Device Address Byte (58h)

ACK

from

aSC7512

ACK

from

aSC7512

SCL

SDA

Start

SMBus Device Address Byte (58h)

R/W

ACK

from

aSC7512

ACK

from

aSC7512

SCL

Stop

Master

ACK

from

aSC7512

Stop

Master

R/W

SDA

Re-start

R/W

SMBus Device Address Byte (58h)

ACK

from

aSC7512

NACK

from

Master

Stop

Master

Pointer Set

(Figure 2.)

without stop by Master

Figure 2 Register Address Pointer Set

Figure 3 Register Write

Figure 4 Register Read

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