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© Andigilog, Inc. 2006
www.andigilog.com
August 2006 - 70A05003
aSC7512
Block Diagram
Pin Descriptions
Symbol
Pin
Type
Name and Function/Connection
SMBDAT
7
Digital I/O
(Open-Drain)
System Management Bus Data. Open-drain output. 5V
tolerant, SMBus 2.0 compliant.
SMBCLK
8
Digital Input
System Management Bus Clock. Tied to Open-drain output.
5V tolerant, SMBus 2.0 compliant.
VDD
1
POWER
+3.3V pin. Can be powered by +3.3V Standby power if
monitoring in low power states is required. This pin should
be bypassed with a 0.1
μF capacitor in parallel with 100pF
GND
5
GROUND
Ground for all analog and digital circuitry.
D+
2
Remote Thermal Diode
Positive Input
Positive input (current source) from the remote thermal
diode serves as the positive input into the A/D. Connected
to the anode of a CPU thermal diode or the base-collector of
a diode connected MMBT3904 NPN transistor.
D-
3
Remote Thermal Diode
Negative Input
Negative input (current sink) from the remote thermal diode
serves as the negative input into the A/D. Connected to
cathode of a CPU thermal diode or the emitter of a diode
connected MMBT3904 NPN transistor.
TACH /
ALERT
6
Digital Input / Digital
Open-Drain Output
Input for monitoring tachometer output of fan (default) or
ALERT
output selectable by configuration register 09h, bit 5.
PWM
4
Digital Open-Drain
Output
Fan speed control, Pulse Width Modulated.
Figure 1 Block Diagram
TACH /
ALERT
D+
D-
Diode
Signal
Con-
ditioning
&
Analog
Mux
ID Registers
Address
Pointer
ADC
Bandgap
Reference
Status Registers
Fan T-min, T-range & T-Hyst
Fan Control Registers
Fan Speed Configuration
SMBus Interface
Limit Registers
Limit Comparators
SMBDAT
SMBCLK
Internal
Sensor
PWM
Fan PWM Control Register
Fan Characteristic Registers
Pin
MUX
Tach Signal
Conditioner
Spike Smoothing
Digital
Filter
Configuration Register
Fan
Speed
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