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MPC18730EPR2 датащи(PDF) 14 Page - Freescale Semiconductor, Inc

номер детали MPC18730EPR2
подробное описание детали  Power Management IC with Five Regulated Outputs Programmed Through 3 Wire Serial Interface
PDF  35 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC18730EPR2 датащи(HTML) 14 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
14
Freescale Semiconductor
18730
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 18730 power management integrated circuit provides
five independent output voltages for the micro controller from
either a single cell Li-Ion or from a single cell Ni-MH or dry
cell. The PMIC includes two DC to DC converters and three
low drop out linear regulators. The output voltage for each of
the five output voltages is set independently through a 3-wire
serial interface. The PMIC has multiple wakeup, sleep, and
reset modes to minimize power consumption for portable
equipment. In single cell Li-Ion applications two DC-DC
converters are configured as buck regulators. In single cell
Ni-MH or dry cell applications, one DC-DC converter is
configured as a boost regulator, and the other as buck-boost
regulator.
FUNCTIONAL PIN DESCRIPTION
CLEAR PIN (CLEAR)
This Clear input signal makes clear internal latches for
WAKE signal holding. The WAKE control circuit can not
receive another WAKE input until the latch is cleared by this
Clear input.
WAKE SIGNAL PINS (WAKE1B, WAKE2B,
WAKE3B, WAKE4B) ... ACTIVE LOW
Any one WAKE input signal of these four WAKE inputs
awakes this device from sleep mode. The WAKE signals can
be made with external low side mechanical switch and
resistance that is pulled up to VSTB rail.
LOW-SIDE SWITCH OUTPUT PIN (LSWO)
Low-Side switch output that is turned on with ‘CLEAR’
signal. It can be used for external key input latches clear.
LOW VOLTAGE BATTERY PIN (LVB)
This input pin is used for temporarily power supply while
wake up for 1cell Ni-MH battery or 1 cell dry cell battery (=
Low Voltage Battery) use. It has to be connected to VB rail.
When Li-Ion battery is used, the pin has to be open.
HIGH VOLTAGE BATTERY PIN (HVB)
This input pin is used for temporarily power supply while
wake up for Li-Ion battery (= High Voltage Battery) use. It has
to be connected to the VB rail. When a Ni-MH battery is used,
the pin has to be connected to ground level.
STANDBY VOLTAGE PIN (V_STDBY)
Standby Voltage is made from LVB or HVB that depends
on which battery is used. This voltage is used for internal
logic and analog circuit at standby (sleep) mode temporarily
before ‘VO1_SENSE’ voltage is established.
VOLTAGE INPUT PINS (VO1_SENSE, VO2_SENSE)
This power supply input pin named ‘VO1_SENS or
VO2_SENSE’ is for internal logic and analog circuits and for
input of ‘VOUT1’ output via power switch. Input for ‘VOUT2’
is ‘VO2_SENSE_IN’ pin. It is supplied from the output of
Channel-1 or Channel-2 DC/DC converter as
‘VO1_SENSEor VO2_SENSE.
VOLTAGE OUTPUT PINS (VOUT1, VOUT2)
Output ‘VO1_SENSE or ‘VO2_SENSE’ voltage controlled
internal power switch.
POWER INPUT PINS (VIN1, VIN2)
The power input pins (VIN1, VIN2) are drain pins on the
top side FET of the DC/DC converter switcher. They are the
power input for the buck converter and output for the boost
converter.
SWITCHING PINS (SW1, SW2)
Switching Pins (SW1, SW2) are the output of the half
bridge and connect to the external inductance.
POWER GROUND PINS (PGND1, PGND2,
GNDGATE)
Ground level node for DC/DC converter and Charge Pump
portion.
INVERTED RESET OUTPUT PINS (PGOOD1,
PGOOD2)
Reset signal output for external MPU or the something
controller. PGOOD1 keeps ‘Low’ level while the
VO1_SENSE voltage is less than internal reference voltage.
PGOOD2 follows to VO2_SENSE voltage.
RESET DELAY CAPACITOR PINS
(PGOOD1_DELAY, PGOOD2_DELAY)
The capacitor connected to this pin decides delay time to
negate the Reset signal from exceeding the reference
voltage level.
RESET 1 ADJUSTMENT PIN (RESET1_TH)
Used to adjust the reset level with external resistance
which is connected to VO1_SENSE for PGOOD1.



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