MPC18730EPR2 datasheet(8/35 Pages) FREESCALE

8 / 35 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

18730

ELECTRICAL CHARACTERISTICS

STATIC

Switching Power Supply 2

VOUT2 Output Voltage (Io = 0~80 mA)

HG Output Voltage (11) (Isource = 400 µA)

(Isink = 400 µA)

LG Output Voltage (11) (Isource = 400 µA)

(Isink = 400 µA)

VOUT2

VDW2TH

VDW2TL

VDW2BH

VDW2BL

1.05

5.2

1.15

1.25

VGATE

0.3

VGATE

0.3

Series Pass Power Supply Circuit

SREG1 Control Voltage (Io = 5~60 mA)

(12)

SREG1-Error AMP Input offset voltage (13)

SREG2 Control Voltage (Io = 6~80 mA)

(12)

SREG2-Error AMP Input offset voltage (14)

SREG3 Control Voltage (Io = 5~60 mA)

(12)

SREG3-Error AMP Input offset voltage (15)

SREG2G Output Voltage (16) (Isource = 2.5 µA)

(Isink = 2.5 µA)

VSREG1

SR1OFST

VSREG2

SR2OFST

VSREG3

SR3OFST

SREG2GH

SREG2GL

2.7

-13.5

2.7

-17

2.7

-11

5.0

2.8

2.9

24.5

2.9

VGATE

0.5

Power Switch On Resistance

VOUT1 Circuit

VOUT2 Circuit

RVOUT1

RVOUT2

0.4

0.6

VGATE Power Supply Circuit

(Io = 0~6 mA)

(17)

(Io = 0~6 mA)

(18)

CH_PUMP Output Voltage (Isource = 2.5 mA)

(Isink = 2.5 mA)

VGH Voltage (Certified value)

VGATE_00

VGATE_10

VO1_SENSE1LH

VO1_SENSE_1LL

VGH

5.5

4.6

VB x 0.85

6.0

5.0

6.5

5.4

0.4

10.5

V_STDBY Output Voltage for Li_ion (Io = 300 µA)

(19)

VLVB

1.75

2.45

Notes

11.

Connect a transistor with gate capacity of 200 pF or smaller to HG and LG

12.

If a capacitor with capacitance of 22 µF is connected to SREGO, use a phase compensation capacitor between SREGO and SREGC

when the load is 5 mA (6 mA for SREG2) or lower. The output voltage values shown in the table assume that external resistance is

connected as follows:

SREGI1 = 3.0 V to 3.3 V, 65.14K

Ω between SREGO1 and SREGC1, 34.86KΩ between SREGC1 and GND.

SREGI2 = 3.0 V to 3.3 V, 54.46K

Ω between SREGO2 and SREGC2, 45.54KΩ between SREGC2 and GND.

SREGI3 = 3.0 V to 3.3 V, 73.84K

Ω between SREGO3 and SREGC3, 26.16KΩ between SREGC3 and GND.

13.

Calculated by the right formula for input offset: SR1OFST = (Vref x 0.77) - (SREGO1

÷ (100k ÷ 34.86k))

14.

Calculated by the right formula for input offset: SR2OFST = (Vref x 1) - (SREGO1

÷ (100k ÷ 45.54k))

15.

Calculated by the right formula for input offset: SR3OFST = (Vref x 0.58) - (SREGO1

÷ (100k ÷ 26.16k))

16.

Connect a transistor with gate capacity of 300 pF or smaller to REG2G.

17.

When VGATESEL1 is Low and VGATESEL2 is Low, I/O = 3 mA or higher is certified by specification.

18.

When VGATESEL1 is High and VGATESEL2 is Low, I/O = 3 mA or higher is certified by specification.

19.

When HVB is 4.2 V and the load from V_STDBY is 0.5

µA or higher.

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions VBATT = 1.2 V, VO1_SENSE = 2.4 V, VGATE= 6.0 V, fCLK = 176.4 kHz unless

otherwise noted. Typical values noted reflect the approximate parameter means at TA = 27°C under nominal conditions unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

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