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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8540CPX667JC датащи(PDF) 20 Page - Freescale Semiconductor, Inc |
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MPC8540CPX667JC датащи(HTML) 20 Page - Freescale Semiconductor, Inc |
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20 / 104 page  MPC8540 Integrated Processor Hardware Specifications, Rev. 4 20 Freescale Semiconductor DDR SDRAM Figure 5 shows the DDR SDRAM output timing diagram. Figure 5. DDR SDRAM Output Timing Diagram 6.2.2.2 Load Effects on Address/Command Bus Table 18 provides approximate delay information that can be expected for the address and command signals of the DDR controller for various loadings. These numbers are the result of simulations for one topology. The delay numbers will strongly depend on the topology used. These delay numbers show the total delay for the address and command to arrive at the DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup requirements at the DRAM. Table 18. Expected Delays for Address/Command Load Delay Unit 4 devices (12 pF) 3.0 ns 9 devices (27 pF) 3.6 ns 36 devices (108 pF) + 40 pF compensation capacitor 5.0 ns 36 devices (108 pF) + 80 pF compensation capacitor 5.2 ns ADDR/CMD DLL Phase Alignment tDDKHOV tDDSHMH tDDKLDS tDDKHDS MDQ[x] MDQS[n] MSYNC_IN MSYNC_OUT MCK[n] MCK[n] tMCK tDDSHME tDDKLDX tDDKHDX tDDSHMP D1 D0 tDDKHOX Write A0 NOOP tMCK tMCKH |
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