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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8540CPX667JC датащи(PDF) 18 Page - Freescale Semiconductor, Inc |
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MPC8540CPX667JC датащи(HTML) 18 Page - Freescale Semiconductor, Inc |
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18 / 104 page  MPC8540 Integrated Processor Hardware Specifications, Rev. 4 18 Freescale Semiconductor DDR SDRAM Figure 3. DDR SDRAM Interface Input Timing 6.2.2 DDR SDRAM Output AC Timing Specifications For chip selects MCS1 and MCS2, there will always be at least 200 DDR memory clocks coming out of self-refresh after an HRESET before a precharge occurs. This will not necessarily be the case for chip selects MCS0 and MCS3. 6.2.2.1 DLL Enabled Mode Table 16 and Table 17 provide the output AC timing specifications and measurement conditions for the DDR SDRAM interface with the DDR DLL enabled. Table 16. DDR SDRAM Output AC Timing Specifications–DLL Mode At recommended operating conditions with GVDD of 2.5 V ± 5%. Parameter Symbol 1 Min Max Unit Notes MCK[n] cycle time, (MCK[n]/MCK[n] crossing) tMCK 610 ns 2 On chip Clock Skew tMCKSKEW — 150 ps 3, 8 MCK[n] duty cycle tMCKH/tMCK 45 55 % 8 ADDR/CMD output valid tDDKHOV —3 ns 4, 9 ADDR/CMD output invalid tDDKHOX 1— ns 4, 9 Write CMD to first MDQS capture edge tDDSHMH tMCK + 1.5 tMCK + 4.0 ns 5 MDQ/MECC/MDM output setup with respect to MDQS 333 MHz 266 MHz 200 MHz tDDKHDS, tDDKLDS 900 1100 1200 —ps 6, 9 MDQ/MECC/MDM output hold with respect to MDQS 333 MHz 266 MHz 200 MHz tDDKHDX, tDDKLDX 900 1100 1200 —ps 6, 9 MDQS preamble start tDDSHMP 0.75 × t MCK + 1.5 0.75 × t MCK + 4.0 ns 7, 8 MDQS[n] MDQ[n] tDISKEW tDISKEW |
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