MPC826XACVR datasheet(13/52 Pages) FREESCALE

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MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

Electrical and Thermal Characteristics

PD = K/(TJ + 273° C)

(2)

Solving equations (1) and (2) for K gives:

K = PD x (TA + 273° C) + θJA x PD

(3)

where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring

PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by

solving equations (1) and (2) iteratively for any value of TA.

2.3.1

Layout Practices

Each VCC pin should be provided with a low-impedance path to the board’s power supply. Each ground

pin should likewise be provided with a low-impedance path to ground. The power supply pins drive

distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four

0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads

and associated printed circuit traces connecting to chip VCC and ground should be kept to less than half an

inch per capacitor lead. A four-layer board is recommended, employing two inner layers as V

CC and GND

planes.

All output pins on the MPC826xA have fast rise and fall times. Printed circuit (PC) trace interconnection

length should be minimized in order to minimize overdamped conditions and reflections caused by these

fast output switching times. This recommendation particularly applies to the address and data buses.

Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all

device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and

bypassing becomes especially critical in systems with higher capacitive loads because these loads create

higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be

inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.

Table 5 provides preliminary, estimated power dissipation for various configurations. Note that suitable

thermal management is required for conditions above PD = 3W (when the ambient temperature is 70° C or

greater) to ensure the junction temperature does not exceed the maximum specified value. Also note that

the I/O power should be included when determining whether to use a heat sink.

Table 5. Estimated Power Dissipation for Various Configurations(1)

Bus

(MHz)

CPM

Multiplier

Core CPU

Multiplier

CPM

(MHz)

CPU

(MHz)

PINT(W)

(2)

Vddl 1.8 Volts

Vddl 2.0 Volts

Nominal

Maximum

Nominal

Maximum

66.66

133

200

1.2

1.8

2.3

66.66

2.5

166

200

1.3

2.1

1.9

2.3

66.66

200

266

—

2.3

2.9

66.66

4.5

200

300

—

2.4

3.1

83.33

166

250

—

2.2

2.8

83.33

166

250

—

2.2

2.8

83.33

2.5

3.5

208

291

—

2.4

3.1

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