MPC855T datasheet(2/80 Pages) FREESCALE

2 / 80 page

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconductor

Features

2Features

The following list summarizes the key MPC860 features:

•

Embedded single-issue, 32-bit PowerPCTM core (implementing the PowerPC architecture) with

thirty-two 32-bit general-purpose registers (GPRs)

— The core performs branch prediction with conditional prefetch without conditional execution.

— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)

– 16-Kbyte instruction caches are four-way, set-associative with 256 sets; 4-Kbyte instruction caches

are two-way, set-associative with 128 sets.

– 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are two-way,

set-associative with 128 sets.

– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache

blocks.

– Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and

are lockable on a cache block basis.

— MMUs with 32-entry TLB, fully-associative instruction, and data TLBs

— MMUs support multiple page sizes of 4-, 16-, and 512-Kbytes, and 8-Mbytes; 16 virtual address spaces

and 16 protection groups

— Advanced on-chip-emulation debug mode

•

Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

•

32 address lines

•

Operates at up to 80 MHz

•

Memory controller (eight banks)

— Contains complete dynamic RAM (DRAM) controller

Table 1. MPC860 Family Functionality

Part

Cache (Kbytes)

Ethernet

ATM

SCC

Reference 1

Supporting documentation for these devices refers to the following:

1. MPC860 PowerQUICC Family User’s Manual (MPC860UM, Rev. 3)

2. MPC855T User’s Manual (MPC855TUM/D, Rev. 1)

Instruction

Cache

Data Cache

10T

10/100

MPC860DE

Up to 2

—

MPC860DT

Up to 2

Yes

MPC860DP

Up to 2

Yes

MPC860EN

Up to 4

—

MPC860SR

Up to 4

—

Yes

MPC860T

Up to 4

Yes

MPC860P

Up to 4

Yes

MPC855T

Yes

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