MPC855T datasheet(3/80 Pages) FREESCALE

3 / 80 page

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconductor

Features

— Each bank can be a chip select or RAS to support a DRAM bank.

— Up to 15 wait states programmable per memory bank

— Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and other memory devices

— DRAM controller programmable to support most size and speed memory interfaces

—Four CAS lines, four WE lines, and one OE line

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

— Variable block sizes (32 Kbyte to 256 Mbyte)

— Selectable write protection

— On-chip bus arbitration logic

•

General-purpose timers

— Four 16-bit timers or two 32-bit timers

— Gate mode can enable/disable counting

— Interrupt can be masked on reference match and event capture.

•

System integration unit (SIU)

— Bus monitor

— Software watchdog

— Periodic interrupt timer (PIT)

— Low-power stop mode

— Clock synthesizer

— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture

— Reset controller

— IEEE 1149.1 test access port (JTAG)

•

Interrupts

— Seven external interrupt request (IRQ) lines

— 12 port pins with interrupt capability

— 23 internal interrupt sources

— Programmable priority between SCCs

— Programmable highest priority request

•

10/100 Mbps Ethernet support, fully compliant with the IEEE 802.3u Standard (not available when using

ATM over UTOPIA interface)

•

ATM support compliant with ATM forum UNI 4.0 specification

— Cell processing up to 50–70 Mbps at 50-MHz system clock

— Cell multiplexing/demultiplexing

— Support of AAL5 and AAL0 protocols on a per-VC basis. AAL0 support enables OAM and software

implementation of other protocols.

— ATM pace control (APC) scheduler, providing direct support for constant bit rate (CBR) and

unspecified bit rate (UBR) and providing control mechanisms enabling software support of available

bit rate (ABR)

— Physical interface support for UTOPIA (10/100-Mbps is not supported with this interface) and

byte-aligned serial (for example, T1/E1/ADSL)

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