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MMA3201DR2 датащи(PDF) 5 Page - Freescale Semiconductor, Inc |
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MMA3201DR2 датащи(HTML) 5 Page - Freescale Semiconductor, Inc |
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5 / 10 page ![]() Sensors Freescale Semiconductor 5 MMA3201D BASIC CONNECTIONS Pinout Description Figure 5. SOIC Accelerometer with Recommended Connection Diagram PCB Layout Figure 6. Recommended PCB Layout for Interfacing Accelerometer to Microcontroller NOTES: 1. Use a 0.1 µF capacitor on VDD to decouple the power source. 2. Physical coupling distance of the accelerometer to the microcontroller should be minimal. 3. Place a ground plane beneath the accelerometer to reduce noise, the ground plane should be attached to all of the open ended terminals shown in Figure 6. 4. Use an RC filter of 1 k Ω and 0.01 µF on the output of the accelerometer to minimize clock noise (from the switched capacitor filter circuit). 5. PCB layout of power and ground should not couple power supply noise. 6. Accelerometer and microcontroller should not be a high current path. 7. A/D sampling rate and any external power supply switching frequency should be selected such that they do not interfere with the internal accelerometer sampling frequency. This will prevent aliasing errors. Pin No. Pin Name Description 1 thru 3 — Leave unconnected. 4 — No internal connection. Leave unconnected. 5 ST Logic input pin used to initiate self-test. 6XOUT Output voltage of the accelerometer. X Direction. 7 STATUS Logic output pin to indicate fault. 8VSS The power supply ground. 9VDD The power supply input. 10 AVDD Power supply input (Analog). 11 YOUT Output voltage of the accelerometer. Y Direction. 12 thru 16 — Used for factory trim. Leave unconnected. 17 thru 19 — No internal connection. Leave unconnected. 20 GND Ground. N/C N/C N/C N/C ST XOUT STATUS VSS VDD AVDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GND N/C N/C N/C N/C N/C N/C N/C N/C YOUT VDD Logic Input C1 0.1 µF 5 9 10 8 ST VDD AVDD VSS YOUT MMA3201D 7 6 11 STATUS X Output Signal R1 1 k Ω C2 0.01 µF R2 1 k Ω C3 0.01 µF Y Output Signal XOUT STATUS ST XOUT YOUT VSS VDD P1 P0 A/D In A/D In VRH VSS VDD C 0.1 µF C0.1 µF Power Supply C 0.1 µF 0.1 µF 0.1 µF R 1 k Ω R C C 1 k Ω |
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