34652 datasheet(20/26 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

34652

TYPICAL APPLICATIONS

Figure 20. External Resistor (RTIMER) Value Versus

Start-Up and Retry Delay Timer Value (tTIMER)

POWER GOOD OUTPUT SIGNALS

The power good pins PG and PG are output pins that are

used to directly enable a power module load. The device has

active high and active low power good output signals.

Choosing which power good active signal depends on the

Enable signal requirement of the load. This feature allows the

34652 to adapt to different applications and a wide variety of

loads.

The power good output signal is active if the Power

MOSFET is fully enhanced and the device is in normal

operation. The signal goes active after a typical 20 ms delay.

The signal deactivates if one of the following occurs:

• Power is turned off.

• The device is disabled for more than 1.0 ms.

• The device exceeded its thermal shutdown threshold for

more than 12

µs.

• The device is in overvoltage or undervoltage mode for

more than 1.0 ms.

• Load current exceeded the overcurrent limit for more than

3.0 ms.

When the power good output signal becomes inactive, it

disables the load, protecting it from any faults or damage.

These loads are usually DC/DC converters, depicted in

Figure 19, page 18. An LED can also be connected to PG to

indicate that the power is good.

The PG and PG pins are referenced to VIN and require a

pull-up resistor connected to VPWR (Figures 18 and 19,

page 18).

DISABLING AND ENABLING THE 34652

The Disable control input (DISABLE) provides two

functions:

• External enable/disable control.

• Manual resetting of the device and the retry counter after

a fault has occurred.

Using the DISABLE pin, a user can enable/disable the 34652

device, which facilitates easy access to connect the load to or

disconnect it from the main power rail.

When power is first applied, the DISABLE pin must be

inactive in order for the 34652 to initiate a start-up sequence.

If the DISABLE pin is active, the device makes no further

steps until the pin is inactive. If the DISABLE pin is activated

at any point during the start-up and thereafter during normal

operation, then the retry counter resets, the Power MOSFET

turns off, and the power good output signals deactivate. The

DISABLE circuit is equipped with a 1.0 ms filter to filter out

any glitches or transients on the DISABLE input and prevent

the Power MOSFET from turning off prematurely.

The DISABLE pin is referenced to VPWR. If left open or

connected to VPWR, meaning the voltage at the DISABLE

pin is between VPWR + 1.2 V and VPWR - 1.2 V, it is inactive

and the device is enabled. If a positive voltage (1.8 V above

VPWR) or a negative voltage (1.8 V below VPWR) is applied to

DISABLE, it is active and the device is disabled.

CHARGING CURRENT LIMIT

When the device passes the UVLO threshold, it checks if

there is any external resistor or external capacitor connected

to the ICHG pin. If there is, then it determines the value of the

charging current limit value and the charging current limit rise

time accordingly. If there is not, it uses the default charging

current limit value of 100 mA and rise time of 1.0 ms.

Note Users are allowed to connect an external capacitor

to the ICHG pin only if an external resistor is also connected.

During the external components’ check, a capacitor produces

an impulse of current and an external resistor will be

detected, even it the external resistor is absent.

When the Power MOSFET is turned on, the current limit is

set gradually from 0 A to ICHG. This current charges up the

load capacitor relatively slowly. When the load capacitor is

fully charged, the Power MOSFET reaches its full

enhancement, which triggers the current limit to change from

ICHG to ILIM and the load current to decrease. The power good

output signals activate after a 20 ms delay, which in turn

enables the load. The 34652 is now in normal operation

mode and the retry counter resets.

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ttim er (ms)

tTIMER (ms)

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