TUSB564 datasheet(32/54 Pages) TI1

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8.2.2.2 Support for DisplayPort UFP_D Pin Assignment E

The TUSB564-Q1 device can be used in a system that handles DisplayPort UFP_D Pin Assignment E use-case

if special measures are taken as described below. With UFP_D Pin Assignment E, the polarity of both the main

link and AUX signals are inverted on the Type-C receptacle pins relative to Pin Assignment C. Moreover, on the

Type-C receptacle, the location of Lane 0 is swapped with Lane 1 and that of Lane 2 is swapped with Lane 3

relative to Pin Assignment C. For correct reception of the DisplayPort video signal, the system must comprehend

the above-described signaling variation.

The use of the TUSB564-Q1 device in a system that handles Pin Assignment E depends on whether AUX-to-

SBU switching of the DisplayPort AUX signal is performed internally by the TUSB564-Q1 or by external devices

such as a PD controller. It also depends on the configuration mode used: I2C Mode or GPIO Mode. In all those

scenarios, the TUSB564-Q1 passes the polarity of the Main Link signals as received. The DisplayPort sink must

handle the polarity inversion of those signals. Moreover, the DisplayPort sink must handle the lane swapping

with the following lane-to-pin mapping as received by the TUSB564-Q1 device: Lane 0 → DP1, Lane 1 → DP0,

Lane 2 → DP3, and Lane 3 → DP2.

The use-case with the AUX-to-SBU switching performed internally by the TUSB564-Q1 device is shown

in Figure 8-3. If the TUSB564-Q1 device configuration is through the I2C Mode, AUX snooping must be

disabled by setting AUX_SNOOP_DISABLE register 0x13[7] = 1'b1, and manual AUX-to-SBU switching must

be performed through the AUX_SBU_OVR register 0x13[5:4]: AUX_SBU_OVR = 2’b01 for normal USB Type-C

plug orientation, or AUX_SBU_OVR = 2’b10 for flipped USB Type-C plug orientation when Pin Assignment E

signals are received. If the TUSB564-Q1 device configuration is through the GPIO Mode, all four DisplayPort

lanes are automatically activated. The DisplayPort sink device must handle the polarity inversion of both the

AUX and Main Link signals as well as main link lane swapping.

SBU1

SBU2

AUXn

AUXp

TUSB564

SBU2

SBU1

AUXP

AUXN

PD Controller

SBU2

SBU1

1M (+/-5%)

AUXP

AUXN

SRC_DET#

SRC_DET

100nF

DP SINK

3.3V

Make AUX connections as short as

possible to minimize stub effects

DP0

DP1

DP2

DP3

TX1

RX1

RX2

TX2

ML0

ML1

ML2

ML3

Figure 8-3. DisplayPort AUX Connections for UFP_D Pin Assignment E with Internal AUX Switching

TUSB564-Q1

SLLSFO9 – MAY 2024

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