Philips Semiconductors Programmable Logic Devices

Product specification

PLHS501/PLHS501I

Programmable macro logic

PML

™

October 22, 1993

11

PLHS501 GATE AND SPEED ESTIMATE TABLE

FUNCTION

INTERNAL NAND

EQUVALENT

COMMENTS

Gates

NANDs

1

6.5ns

For 1 to 32 input variables

ANDs

1

6.5ns

For 1 to 32 input variables

NORs

1

6.5ns

For 1 to 32 input variables

ORs

1

6.5ns

For 1 to 32 input variables

Decoders

3-to-8

8

11ns

Inverted inputs available

4-to-16

16

11ns

Inverted inputs available

5-to-32

32

11ns

Inverted inputs available (24 chip outputs only)

Encoders

8-to-3

15

11ns

Inverted inputs, 2 logic levels

16-to-4

32

11ns

Inverted inputs, 2 logic levels

32-to-5

41

11ns

Inverted inputs, 2 logic levels, factored solution.

Multiplexers

4-to-1

5

11ns

Inverted inputs available

8-to-1

9

11ns

16-to-1

17

11ns

27-to-1

28

11ns

Can address only 27 external inputs - more if internal

Flip-Flops

D-type Flip-Flop

6

30MHz

With asynchronous S-R

T-type Flip-Flop

6

30MHz

With asynchronous S-R

J-K-type Flip-Flop

10

30MHz

With asynchronous S-R

Adders

8-bit

45

15.5ns

Full carry-lookahead (four levels of logic)

Barrel Shifters

8-bit

72

11ns

2 levels of logic

Latches

D-latch

3

2 levels of logic with one shared gate