AD9865-EB datasheet(22/48 Pages) AD

22 / 48 page

AD9865

Rev. A | Page 22 of 48

SCLK

SDATA

SCLK

SDATA

R/W N1

D71 D61

D1N D0N

R/W

D01 D11

D7N

D6N

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

SEN

Figure 45. SPI Timing, MSB First (Upper), and LSB First (Lower)

When the SPI LSB first bit is set high, the serial port interprets

both instruction and data bytes LSB first. Multibyte data trans-

fers in LSB format can be completed by writing an instruction

byte that includes the register address of the first address to be

accessed. The AD9865 automatically increments the address for

each successive byte required for the multibyte communication

cycle.

Figure 46 illustrates the timing requirements for a write opera-

tion to the SPI port. After the serial port enable (SEN) signal

goes low, data (SDIO) pertaining to the instruction header is

read on the rising edges of the clock (SCLK). To initiate a write

operation, the read/not-write bit is set low. After the instruction

header is read, the eight data bits pertaining to the specified

next eight clock cycles. If a multibyte communication cycle is

specified, the destination address is decremented (MSB first)

and shifts in another eight bits of data. This process repeats until

all the bytes specified in the instruction header (N1, N0 bits) are

shifted into the SDIO pin. SEN must remain low during the data

transfer operation, only going high after the last bit is shifted

into the SDIO pin.

SEN

SCLK

SDIO

fSCLK

tLOW

tHI

tDS

tDH

R/W

Figure 46. SPI Write Operation Timing

Figure 47 illustrates the timing for a 3-wire read operation to

the SPI port. After SEN goes low, data (SDIO) pertaining to the

instruction header is read on the rising edges of SCLK. A read

operation occurs, if the read/not-write indicator is set high.

After the address bits of the instruction header are read, the

eight data bits pertaining to the specified register are shifted out

of the SDIO pin on the falling edges of the next eight clock cycles.

If a multibyte communication cycle is specified in the instruction

header, a similar process as previously described for a multibyte

SPI write operation applies. The SDO pin remains three-stated

in a 3-wire read operation.

SEN

SCLK

SDIO

fSCLK

tLOW

tHI

tDS

tDH

R/W

tEZ

tDV

Figure 47. SPI 3-Wire Read Operation Timing

Figure 48 illustrates the timing for a 4-wire read operation to

the SPI port. The timing is similar to the 3-wire read operation

with the exception that data appears at the SDO pin, while the

SDIO pin remains high impedance throughout the operation.

The SDO pin is an active output only during the data transfer

phase and remains three-stated at all other times.

SEN

SCLK

SDIO

fSCLK

tLOW

tHI

tDS

tDH

R/W

tEZ

tDV

SDO

tEZ

Figure 48. SPI 4-Wire Read Operation Timing

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