AD9865-EB datasheet(7/48 Pages) AD

7 / 48 page

AD9865

Rev. A | Page 7 of 48

SERIAL PORT TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 5.

Parameter

Temp

Test Level

Min

Typ

Max

Unit

WRITE OPERATION (See Figure 46)

SCLK Clock Rate (fSCLK)

Full

MHz

SCLK Clock High (tHI)

Full

SCLK Clock Low (tLOW)

Full

SDIO to SCLK Setup Time (tDS)

Full

SCLK to SDIO Hold Time (tDH)

Full

SEN to SCLK Setup Time (tS)

Full

SCLK to SEN Hold Time (tH)

Full

READ OPERATION (See Figure 47 and Figure 48)

SCLK Clock Rate (fSCLK)

Full

MHz

SCLK Clock High (tHI)

Full

SCLK Clock Low (tLOW)

Full

SDIO to SCLK Setup Time (tDS)

Full

SCLK to SDIO Hold Time (tDH)

Full

SCLK to SDIO (or SDO) Data Valid Time (tDV)

Full

SEN to SDIO Output Valid to Hi-Z (tEZ)

Full

HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 6.

Parameter

Temp

Test Level

Min

Typ

Max

Unit

READ OPERATION1 (See Figure 50)

Output Data Rate

Full

MSPS

Three-State Output Enable Time (tPZL)

Full

Three-State Output Disable Time (tPLZ)

Full

Rx Data Valid Time (tVT)

Full

1.5

Rx Data Output Delay (tOD)

Full

WRITE OPERATION (See Figure 49)

Input Data Rate (1× Interpolation)

Full

MSPS

Input Data Rate (2× Interpolation)

Full

MSPS

Input Data Rate (4× Interpolation)

Full

MSPS

Tx Data Setup Time (tDS)

Full

Tx Data Hold Time (tDH)

Full

2.5

Latch Enable Time (tEN)

Full

Latch Disable Time (tDIS)

Full

1 CLOAD = 5 pF for digital data outputs.

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