AD9995KCPRL datasheet(39/60 Pages) AD

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AD9995

–39–

Updating New Register Values

The AD9995’s internal registers are updated at different times,

depending on the particular register.Table XV summarizes the

four different types of register updates:

1. SCK Updated: Some of the registers in Bank 1 are updated

immediately, as soon as the 24th data bit (D23) is written.

These registers are used for functions that do not require gat-

ing with the next VD boundary, such as power-up and reset

functions.These registers are lightly shaded in gray in the

Bank 1 register list.

The Bank Select register (Addr. 0x7F in Bank 1 and 2) is also

SCK updated.

2. VD Updated: Most of the registers in Bank 1, as well as the

Field registers in Bank 2, are updated at the next VD falling

edge. By updating these values at the next VD edge, the cur-

rent field will not be corrupted and the new register values

will be applied to the next field. The Bank 1 register updates

may be further delayed past the VD falling edge by using

the UPDATE register (Addr. 0x19). This will delay the VD

updated register updates to any HD line in the field. Note that

the Bank 2 registers are not affected by the UPDATE register.

3. SG-Line Updated: A few of the registers in Bank 1 are

updated at the end of the SG active line, at the HD falling

edge.These are the registers to control the SUBCK signal so

that the SUBCK output will not be updated until after the SG

line has been completed.These registers are darkly shaded in

gray in the Bank 1 register list.

4. SCP Updated: In Bank 2, all of the V-pattern group and

V-sequence registers (Addr. 0x00 through 0xCF, exclud-

ing 0x7F) are updated at the next SCP, where they will

be used. For example, in Figure 42, this field has selected

Region 1 to use V-Sequence 3 for the vertical outputs. This

means that a write to any of the V-Sequence 3 registers, or

any of the V-pattern group registers that are referenced by

V-Sequence 3 will be updated at SCP1. If multiple writes

are done to the same register, the last one done before SCP1

will be the one that is updated. Likewise, register writes to

any V-Sequence 5 registers will be updated at SCP2, and

at SCP3.

Table XV. Register Update Locations

Update Type

Description

SCK Updated

Bank 1 Only

VD Updated

Bank 1 and Bank 2

delayed further by using the UPDATE register at Address 0x19 in Bank 1. Bank 2

updates will not be affected by the UPDATE register.

SG Line Updated

Bank 1 Only

SCP Updated

Bank 2 Only

REGION 0

SCP 1

SCP 2

SCP 3

REGION 1

REGION 2

REGION 3

VSG

SGLINE

SCP 0

SERIAL

WRITE

SCK

UPDATED

SCP 0

UPDATED

SCP

UPDATED

V1–V6

USE VSEQ2

USE VSEQ3

USE VSEQ5

USE VSEQ8

Figure 42. Register Update Locations (SeeTable XV for Definitions)

REV. 0

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