M68HC08 datasheet(97/124 Pages) FREESCALE

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5.0-Volt Serial Peripheral Interface Timing

MC68HC05C9A Advance Information Data Sheet, Rev. 5.1

Freescale Semiconductor

12.9 5.0-Volt Serial Peripheral Interface Timing

No.

Characteristic(1)

Symbol

Min

Max

Unit

Operating frequency

Master

Slave

fOP(M)

fOP(S)

0.5

2.1

fOP

MHz

Cycle time

Master

Slave

tCYC(M)

tCYC(S)

2.0

480

—

tCYC

Enable lead time

Master

Slave

tLead(M)

tLead(S)

Note(2)

240

—

Enable lag time

Master

Slave

tLag(M)

tLag(S)

Note(2)

720

—

Clock (SCK) high time

Master

Slave

tW(SCKH)M

tW(SCKH)S

340

190

—

Clock (SCK) low time

Master

Slave

tW(SCKL)M

tW(SCKL)S

340

190

—

Data setup time (inputs)

Master

Slave

tSU(M)

tSU(S)

100

—

Data hold time (inputs)

Master

Slave

tH(M)

tH(S)

100

—

Slave access time (time to data active from

high-impedance state)

120

Slave disable time (hold time to high-impedance state)

tDIS

—

240

Data Valid

Master (before capture edge)

Slave (after enable edge)(3)

tV(M)

tV(S)

0.25

—

240

tCYC(M)

Data hold time (outputs)

Master (after capture edge)

Slave (after enable edge)

tHO(M)

tHO(S)

0.25

—

tCYC(M)

Rise time (20% VDD to 70% VDD, CL = 200 pF)

SPI outputs (SCK, MOSI, and MISO)

SPI inputs (SCK, MOSI, MISO, and SS)

tRM

tRS

—

100

2.0

µs

Fall time (70% VDD to 20% VDD, CL = 200 pF)

SPI outputs (SCK, MOSI, and MISO)

SPI inputs (SCK, MOSI, MISO, and SS)

tFM

tFS

—

100

2.0

µs

1. VDD = 5.0 Vdc ± 10%; VSS = 0 Vdc, TA = –40 to +125°C, unless otherwise noted. Refer to Figure 12-9 and Figure 12-10

for timing diagrams.

2. Signal production depends on software.

3. Assumes 200 pF load on all SPI pins

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