M68HC08 datasheet(49/124 Pages) FREESCALE

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Timer I/O Registers

MC68HC05C9A Advance Information Data Sheet, Rev. 5.1

Freescale Semiconductor

8.3.3 Timer Registers

The timer registers (TRH and TRL), shown in Figure 8-4, contain the current high and low bytes of the

16-bit counter. Reading TRH before reading TRL causes TRL to be latched until TRL is read. Reading

TRL after reading the timer status register clears the timer overflow flag (TOF). Writing to the timer

registers has no effect.

8.3.4 Alternate Timer Registers

The alternate timer registers (ATRH and ATRL), shown in Figure 8-5, contain the current high and low

bytes of the 16-bit counter. Reading ATRH before reading ATRL causes ATRL to be latched until ATRL

is read. Reading ATRL has no effect on the timer overflow flag (TOF). Writing to the alternate timer

registers has no effect.

Figure 8-5. Alternate Timer Registers (ATRH and ATRL)

NOTE

To prevent interrupts from occurring between readings of ATRH and ATRL,

set the interrupt flag in the condition code register before reading ATRH,

and clear the flag after reading ATRL.

Address:

$0018 — TRH

Bit 7

654321

Bit 0

Read:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Write

Reset:

11111111

Address:

$0019 — TRL

Bit 7

654321

Bit 0

Read:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Write:

Reset:

11111100

= Unimplemented

Figure 8-4. Timer Registers (TRH and TRL)

Address:

$001A — ATRH

Bit 7

654321

Bit 0

Read:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Write:

Reset:

11111111

Address:

$001B — ATRL

Bit 7

654321

Bit 0

Read:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Write:

Reset:

11111100

= Unimplemented

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