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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TVP7002PZP датащи(PDF) 18 Page - Texas Instruments |
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TVP7002PZP датащи(HTML) 18 Page - Texas Instruments |
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18 / 52 page  www.ti.com TVP7002 SLES206 – MAY 2007 If activity is not detected on either the HSYNC input or the VSYNC input, the host processor should assume that the PC graphics input is configured as a standard 3-wire interface. In this case, the TVP7002 is automatically configured for a SOG input. VSYNC Input HSYNC Input PC Graphics Activity Detect Activity Detect Input Type 1 1 5 wire (default) 1 0 Undefined (assume 5 wire) 0 1 4 wire 0 0 3 wire The activity detection status for the VSYNC and HSYNC inputs is written to the I2C status register at subaddress 14h. NOTE: Pin 13 of a standard 15-pin VGA video connect can be either a horizontal sync (HSYNC) or a composite sync (CSYNC). NOTE: For component video inputs, the active HSYNC and VSYNC should always be derived from the selected SOG input. This can most easily be ensured by setting the AHSO, AVSO, AHSS and AVSS bit fields in register 0Eh to logic 1. NOTE: For proper operation when separate HSYNC and VSYNC inputs are used, the leading edge of VSYNC must not be presicely aligned with the leading edged of HSYNC. A simple RC delay circuit will provide adequate delay in most applications. Figure 5. Sync Processing 18 Submit Documentation Feedback |
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