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TVP7002PZP датащи(PDF) 45 Page - Texas Instruments |
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TVP7002PZP датащи(HTML) 45 Page - Texas Instruments |
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45 / 52 page ![]() www.ti.com Clocks Per Line Status HSYNC Width VSYNC Width Line Length Tolerance Reserved TVP7002 SLES206 – MAY 2007 Subaddress 39h–3Ah Read only Subaddress 7 6 5 4 3 2 1 0 39h Clocks per Line [7:0] 3Ah Reserved Clocks per Line [11:8] Clocks per Line [11:0]: Number of clock cycles per line. The value written to this register represents the length of the longest line per frame. A known timing reference based on either the internal clock reference (~6.3 MHz) or an external clock reference input (EXT_CLK) of up to 27 MHz may be selected using subaddress 1Ah. The clocks per line value may be used to determine the horizontal frequency (fH) of the video input. fH = clock reference frequency / clocks per line Note: The Clocks per Line counter is not dependent on the H-PLL being locked. Subaddress 3Bh Read only 7 6 5 4 3 2 1 0 HSYNC width [7:0] HSYNC width [7:0]: Number of clock cycles between the leading and trailing edges of the HSYNC input. A known timing reference based on either the internal clock reference (~6.3 MHz) or an external clock reference input (EXT_CLK) of up to 27 MHz may be selected using subaddress 1Ah. Note: The HSYNC width counter is not dependent on the H-PLL being locked. Subaddress 3Ch Read only 7 6 5 4 3 2 1 0 Reserved VSYNC width [4:0] VSYNC width [4:0]: Number of lines between the leading and trailing edges of the VSYNC input. The VSYNC width along with the HSYNC and VSYNC polarities can be used to determine whether the input graphics format is using VESA-CVT generated timings. Note: The VSYNC width counter is not dependent on the H-PLL being locked. Subaddress 3Dh Default (03h) 7 6 5 4 3 2 1 0 Reserved Line length tolerance [6:0] Line length tolerance [6:0]: Controls sensitivity to HSYNC input stability when using either the internal or external clock reference. Increasing the line length tolerance may be required for input signals having horizontal instability. Effects the clock cycles per line counter (see subaddresses 39h–3Ah) 00h = No tolerance (minimum) 03h = 3 line length tolerance (default) 7Fh = 127 line length tolerance (maximum) Subaddress 3Eh Default (04h) 7 6 5 4 3 2 1 0 Reserved [7:0] Reserved [7:0]: 04h = Required setting (default) 45 Submit Documentation Feedback |
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