DSP56853 datasheet(13/60 Pages) FREESCALE

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Introduction

56853 Technical Data, Rev. 6

Freescale Semiconductor

Input/Output(Z)

Data Bus (D0-D15)—These pins provide the bidirectional data for

external program or data memory accesses.

107

108

109

110

111

D10

122

D11

123

D12

126

D13

127

D14

128

D15

Output

Read Enable (RD) —is asserted during external memory read cycles.

This signal is pulled high during reset.

Output

Write Enable (WR)— is asserted during external memory write

cycles.

This signal is pulled high during reset.

CS0

GPIOA0

Output

Input/Output

External Chip Select (CS0)—This pin is used as a dedicated GPIO.

Port A GPIO (0) —This pin is a General Purpose I/O (GPIO) pin when

not configured for host port usage.

CS1

GPIOA1

Output

Input/Output

External Chip Select (CS1)—This pin is used as a dedicated GPIO.

Port A GPIO (1) —This pin is a General Purpose I/O (GPIO) pin when

not configured for host port usage.

CS2

GPIOA2

Output

Input/Output

External Chip Select (CS2)—This pin is used as a dedicated GPIO.

Port A GPIO (2) —This pin is a General Purpose I/O (GPIO) pin when

not configured for host port usage.

CS3

GPIOA3

Output

Input/Output

External Chip Select (CS3)—This pin is used as a dedicated GPIO.

Port A GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when

not configured for host port usage.

Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No.

Signal Name

Type

Description

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