DSP56F802 datasheet(3/40 Pages) FREESCALE

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56F802 Technical Data, Rev. 9

Freescale Semiconductor

56F802 Block Diagram

JTAG/

OnCE

Port

Digital Reg

Analog Reg

Low Voltage

Supervisor

Program Controller

and

Hardware Looping Unit

Data ALU

16 x 16 + 36

→ 36-Bit MAC

Three 16-bit Input Registers

Two 36-bit Accumulators

Address

Generation

Unit

Bit

Manipulation

Unit

16-Bit

56800

Core

PAB

PDB

XDB2

CGDB

XAB1

XAB2

INTERRUPT

CONTROLS

IPBB

CONTROLS

IPBus Bridge

(IPBB)

MODULE CONTROLS

ADDRESS BUS [8:0]

DATA BUS [15:0]

COP RESET

RESET

Applica-

tion-Specific

Memory &

Peripherals

Interrupt

Controller

Program Memory

8188 x 16 Flash

1024 x 16 SRAM

Boot Flash

2048x 16 Flash

Data Memory

2048 x 16 Flash

1024 x 16 SRAM

COP/

Watchdog

SCI0

GPIO

Quad Timer D

or GPIO

Quad Timer C

A/D1

A/D2

ADC

PWM Outputs

PWMA

VCAPC VDD

VSS*VDDA

VSSA

•

VREF

PLL

Relaxation

Oscillator

*includes TCS pin which is reserved for factory use and is tied to VSS

Fault A0

• Up to 30 MIPS operation at 60MHz core frequency

• Up to 40 MIPS operation at 80MHz core frequency

• DSP and MCU functionality in a unified,

C-efficient architecture

• MCU-friendly instruction set supports both DSP and

controller functions: MAC, bit manipulation unit, 14

addressing modes

• Hardware DO and REP loops

• 6-channel PWM Module with fault input

• Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel)

• Serial Communications Interface (SCI)

• Two General Purpose Quad Timers with 2 external

outputs

•8K

× 16-bit words (16KB) Program Flash

•1K

× 16-bit words (2KB) Program RAM

•2K

× 16-bit words (4KB) Data Flash

•1K

× 16-bit words (2KB) Data RAM

•2K

× 16-bit words (4KB) Boot Flash

• JTAG/OnCETM port for debugging

• On-chip relaxation oscillator

• 4 shared GPIO

• 32-pin LQFP Package

56F802 General Description

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