CS42435-DMZ datasheet(47/58 Pages) CIRRUS

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DS685F1

CS42435

7.12 ADC Channel Invert (Address 17h)

7.12.1 Invert Signal Polarity (INV_AINX)

Default = 0

0 - Disabled

1 - Enabled

Function:

When enabled, these bits will invert the signal polarity of their respective channels.

7.13 Status (Address 19h) (Read Only)

For all bits in this register, a “1” means the associated error condition has occurred at least once since the

of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated

mask register will always be “0” in this register.

7.13.1 CLOCK ERROR (CLK ERROR)

Default = x

Function:

Indicates an invalid MCLK to FS ratio. This status flag is set to “Level Active Mode” and becomes active

during the error condition. See “System Clocking” on page 32 for valid clock ratios.

7.13.2 ADC Overflow (ADCX_OVFL)

Default = x

Function:

Indicates that there is an over-range condition anywhere in the CS42435 ADC signal path of each of the

associated ADC’s.

Binary Code

Volume Setting

0111 1111

+24 dB

···

0011 0000

+24 dB

···

0000 0000

0 dB

1111 1111

-0.5 dB

1111 1110

-1 dB

···

1000 0000

-64 dB

Table 7. Example AIN Volume Settings

432

Reserved

INV_A4

INV_A3

INV_A2

INV_A1

Reserved

CLK Error

Reserved

ADC2_OVFL

ADC1_OVFL

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