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CDCE401

SCAS820 – JUNE 2006

TIMING REQUIREMENTS (continued)

over recommended ranges of supply voltage, load, and operating free-air temperature

PARAMETER

MIN

NOM

MAX

UNIT

OG0 = 1

OG1 = 1

25

Base input capacitance into XOUT,

OG0 = 1

OG1 = 0

17

pF

OG0 = 0

OG1 = 1

16

off

OG0 = 0

OG1 = 0

11

CXx7

6

CXx6

3

pF

CXx5

1.5

Crystal tune capacitance, measured single-ended against

CXx4

0.75

CXI[7:0]

CXO[7:0]

CXx3

375

CXx2

187

fF

CXx1

94

CXx0

47

FOUT OUTPUT PARAMETER

Crystal frequency

20

100

MHz

Rise and fall time

10% to 90% VDD and

2

3

ns

Highest output frequency

100

MHz

Load capacitance

15

pF

At VDD/2, 20 MHz

≤ freq ≤ 80

45%

50%

55%

MHz

odc

Output duty cycle

At VDD/2, 80 MHz < freq

≤

40%

50%

60%

100MHz

SDATA/EN TIMING

Repeat frequency of programming

200

kHz

LOW signal: high-pulse duration

0.5

1

1.2

µs

LOW signal: low-pulse duration while entering programming sequence

3.8

4

4.2

µs

LOW signal: low-pulse duration while programming bits

3.8

HIGH signal: high-pulse duration

3.8

4

4.5

µs

HIGH signal: low-pulse duration while entering programming sequence

0.5

1

1.2

µs

HIGH signal: low-pulse duration while programming bits

0.5

Time delay between SDATA signal and SDATA_Delayed signal at VDD = 3.3 V

1.5

2.5

3.5

µs

Time between bits during enter programming mode and enter read-back mode

10

30

µs

beyond which a time-out must occur

EN high time before first SDATA can be clocked in

60

µs

EN low time before first SDATA bit is clocked in

2

10

µs

Rise and fall time from 20% to 80% of VDD

1

15

ns

12

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