TMS320VC5402 datasheet(49/68 Pages) TI

49 / 68 page

TMS320VC5402

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

HOLD and HOLDA timings

timing requirements for memory control signals and HOLDA, [H = 0.5 tc(CO)] (see Figure 21)

MIN

MAX

UNIT

tw(HOLD)

Pulse duration, HOLD low

4H+7

tsu(HOLD)

Setup time, HOLD low/high before CLKOUT low

switching characteristics over recommended operating conditions for memory control signals

and HOLDA, [H = 0.5 tc(CO)] (see Figure 21)

PARAMETER

MIN

MAX

UNIT

tdis(CLKL-A)

Disable time, address, PS, DS, IS high impedance from CLKOUT low

tdis(CLKL-RW)

Disable time, R/W high impedance from CLKOUT low

tdis(CLKL-S)

Disable time, MSTRB, IOSTRB high impedance from CLKOUT low

ten(CLKL-A)

Enable time, address, PS, DS, IS from CLKOUT low

2H+5

ten(CLKL-RW)

Enable time, R/W enabled from CLKOUT low

2H+5

ten(CLKL-S)

Enable time, MSTRB, IOSTRB enabled from CLKOUT low

2H+5

Valid time, HOLDA low after CLKOUT low

–1

tv(HOLDA)

Valid time, HOLDA high after CLKOUT low

–1

tw(HOLDA)

Pulse duration, HOLDA low duration

2H–1

IOSTRB

MSTRB

R/W

D[15:0]

PS, DS, IS

A[19:0]

HOLDA

HOLD

CLKOUT

ten(CLKL-S)

ten(CLKL-RW)

tdis(CLKL-S)

tdis(CLKL-RW)

tdis(CLKL-A)

tv(HOLDA)

tw(HOLDA)

tw(HOLD)

tsu(HOLD)

ten(CLKL-A)

Figure 21. HOLD and HOLDA Timings (HM = 1)

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