ADPD7008 datasheet(52/71 Pages) AD

52 / 71 page

Data Sheet

ADPD7008

analog.com

Rev. 0 | 52 of 71

Table 16. Register Details (Continued)

Reg

Name

Bits Bit Name

Description

Reset

Access

[14:

OSC_32M_CAL_COUNT

High frequency oscillator calibration count. This

cycles that occurred during the last high frequency

oscillator calibration cycle.

0x0

0x00B

OSC960K

CAPTURE_TIMESTAMP

Enables time stamp capture. This bit is used to

arm the time stamp capture function. When set,

the next rising edge on the time stamp input

(defaults to GPIO0) causes a time stamp capture.

This bit is cleared when the time stamp occurs.

0x0

R/W

[14:

12]

RESERVED

Reserved.

0x0

OSC_960K_EFUSE_CTRL

Enables the frequency oscillator frequency

control from the eFuse bits. Write 0 to this

bit to enable the frequency control from the

OSC_960K_FREQ_ADJ bits.

0x1

R/W

OSC_CAL_ENABLE

Enables clock calibration clocking. Writing a 1 to

this bit enables the clocking of the low frequency

and high frequency calibration circuits.

0x0

R/W

[9:0] OSC_960K_FREQ_ADJ

Low frequency oscillator frequency control. 0x000

is the lowest frequency, and 0x3FF is the

maximum frequency.

0x2B2

R/W

0x00D

TS_FREQ

[15:

TIMESLOT_PERIOD_L

Lower 16 bits of time slot period in low frequency

oscillator cycles. The time slot rate is (timer clock

frequency)/(TIMESLOT_PERIOD_x). The default

value operates at 100 Hz when using the 960

kHz clock. If the timer clock is set as an external

source from the GPIO, either 960 kHz or 32 kHz,

TM_CLK_GPIO_SEL must be configured to match

the real clock frequency.

0x2580

R/W

0x00E

TS_FREQH

[15:

RESERVED

Reserved.

0x0

[6:0] TIMESLOT_PERIOD_H

Upper seven bits of time slot period in low

frequency oscillator cycles. The time slot rate is

(timer clock frequency)/(TIMESLOT_PERIOD_x).

The default value operates at 100 Hz when using

the 960 kHz clock. If the timer clock is set to be an

external source from the GPIO, either 960 kHz or

32 kHz, TM_CLK_GPIO_SEL must be configured

to match the real clock frequency.

0x0

R/W

0x00F

SYS_CTL

SW_RESET

Software Reset. Write 1 to this bit to assert

a software reset. This resets the chip to its

default values and stopping all analog front end

operations. It does not reset the SPI (or optional

I2C) port. The write to this register completes

normally.

0x0

R0/W

[14:

12]

RESERVED

Reserved.

0x0

RESERVED

Reserved.

0x0

[10:

ALT_CLOCKS

External clock select.

0x0

R/W

000: uses internal clocks.

001: uses GPIO for low frequency oscillator (960

kHz). Timer clock also uses this as source.

ADPD7008 датащи(PDF) 52 Page - Analog Devices

ADPD7008 датащи(HTML) 52 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

датащи скачать

ссылки URL