ADPD7008 datasheet(49/71 Pages) AD

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Data Sheet

ADPD7008

analog.com

Rev. 0 | 49 of 71

Table 16. Register Details

Reg

Name

Bits Bit Name

Description

Reset

Access

0x000

FIFO_STATUS

CLEAR_FIFO

Clear FIFO. Write a 1 to empty the FIFO while not

operating, which resets the FIFO_BYTE_COUNT

and also clears the FIFO overflow, FIFO

underflow, and FIFO threshold interrupt status bits.

0x0

R0/W

INT_FIFO_UFLOW

FIFO underflow error. This bit is set when the

FIFO is read when it was empty. Write 1 to this bit

to clear the interrupt, and it is also cleared when

the FIFO is cleared by using the CLEAR_FIFO

0x0

R/W1C

INT_FIFO_OFLOW

FIFO overflow error. This bit is set when data

is not written to the FIFO due to lack of space.

Write 1 to this bit to clear the interrupt, which

is also cleared if the FIFO is cleared with the

CLEAR_FIFO register bit.

0x0

R/W1C

INT_FIFO_TH

FIFO_TH interrupt status. This bit is set during a

FIFO write when the number of bytes in the FIFO

exceeds the FIFO_TH register value. Write 1 to

this bit to clear this interrupt. This bit can also be

automatically cleared when the FIFO data register

is read if the INT_ACLEAR_FIFO bit is set.

0x0

R/W1C

FIFO_INIT_DONE_STATUS

FIFO initialization process is finished. Note that

this field is a status bit and is not sent to interrupt.

This bit is set after the FIFO self-initialization

process.

0x0

[10:

FIFO_BYTE_COUNT

Number of bytes in the FIFO. This field indicates

the number of bytes in the FIFO.

0x0

0x001

INT_STATUS_TS1

[15:

12]

RESERVED

Reserved.

0x0

INT_PPG_LEV0_L

PPG Time Slot L Level 0 interrupt status. This

bit is set during a data register update when the

configured criteria is met. This bit is set when the

Channel 1 TIA saturates during Time Slot L.

0x0

R/W1C

INT_PPG_LEV0_K

PPG Time Slot K Level 0 interrupt status. This

bit is set during a data register update when the

configured criteria is met. This bit is set when the

Channel 1 TIA saturates during Time Slot K.

0x0

R/W1C

INT_PPG_LEV0_J

PPG Time Slot J Level 0 interrupt status. This

bit is set during a data register update when the

configured criteria is met. This bit is set when the

Channel 1 TIA saturates during Time Slot J.

0x0

R/W1C

INT_PPG_LEV0_I

PPG Time Slot I Level 0 interrupt status. This

bit is set during a data register update when the

configured criteria is met. This bit is set when the

Channel 1 TIA saturates during Time Slot I.

0x0

R/W1C

INT_PPG_LEV0_H

PPG Time Slot H Level 0 interrupt status. This

bit is set during a data register update when the

configured criteria is met. This bit is set when the

Channel 1 TIA saturates during Time Slot H.

0x0

R/W1C

INT_PPG_LEV0_G

PPG Time Slot G Level 0 interrupt status. This

bit is set during a data register update when the

configured criteria is met. This bit is set when the

Channel 1 TIA saturates during Time Slot G.

0x0

R/W1C

INT_PPG_LEV0_F

PPG Time Slot F Level 0 interrupt status. This

bit is set during a data register update when the

0x0

R/W1C

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