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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AMD-K6-2E/233AMZ датащи(PDF) 32 Page - Advanced Micro Devices |
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AMD-K6-2E/233AMZ датащи(HTML) 32 Page - Advanced Micro Devices |
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32 / 332 page  14 Internal Architecture Chapter 2 AMD-K6™-2E Processor Data Sheet 22529B/0—January 2000 Preliminary Information Figure 3. The Instruction Buffer Instruction Decode The AMD-K6-2E processor decode logic is designed to decode multiple x86 instructions per clock (see Figure 4 on page 15). The decode logic accepts x86 instruction bytes and their predecode bits from the instruction buffer, locates the actual instruction boundaries, and generates RISC86 operations from these x86 instructions. RISC86 operations are fixed-format internal instructions. Most RISC86 operations execute in a single clock. RISC86 operations are combined to perform every function of the x86 instruction set. Some x86 instructions are decoded into as few as zero RISC86 opcodes, for instance a NOP, or one RISC86 operation, a register-to-register add. More complex x86 instructions are decoded into several RISC86 operations. 16 Instruction Bytes plus 16 Sets of Predecode Bits Branch-Target Cache 16 x 16 Bytes 2:1 Instruction Buffer 16 Bytes 16 Bytes Branch Target Address Adders Return Address Stack 16 x 16 Bytes 32-Kbyte Level-One Instruction Cache Fetch Unit |
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