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AD8156ABCZ датащи(PDF) 16 Page - Analog Devices |
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AD8156ABCZ датащи(HTML) 16 Page - Analog Devices |
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16 / 20 page ![]() AD8156 Rev. 0 | Page 16 of 20 ADDRESS PINS, A[3:0] INPUTS The AD8156 feature sets can be set port by port or globally. A[3:2] specify what is being programmed or read back when the part is being configured port by port. Connectivity, output current, equalization, or global programming features are chosen based on the values of A[3:2]. Similarly, A[1:0] address the port that is being programmed or read back. In global programming, A[1:0] serve a different function. Refer to Table 9 to Table 15 for programming examples. DATA PINS, D[3:0] INPUTS/OUTPUTS In readback mode, the D[3:0] pins are low impedance outputs indicating the stored values in the memory to be read. The readback drivers are designed to drive high impedances only, so external drivers connected to D[3:0] must be disabled during readback mode. CONTROL INTERFACE LEVELS The AD8156 control interface shares the data path supply pins, VCC and VEE. The potential between the positive logic supply VCC and the negative supply VEE must be at least 3.0 V and no more than 3.7 V. Regardless of supply, the logic threshold is approximately one-half the supply range, allowing the interface to be used with most LVCMOS- and LVTTL-logic drivers. Table 7. Dual 2 × 2 Mode Programming Table Address A[3:0] Data D[3:0] Input A3 to Input A0 enable Output 3 to Output 0, respectively. Input D3 to Input D0 control the connectivity of Output 3 to Output 0, respectively. 1 = Enables the output (for all A[3:0] inputs) 0 = Input 2, 1 = Input 3 (for D2 and D3) 0 = Disables the output (for all A[3:0] inputs) 0 = Input 0, 1 = Input 1 (for D0 and D1) Table 8. 4 × 4 Mode Programming Table Mode Address A[3:0] Data D[3:0] 0 0 A1 A0 0 D2 D1 D0 Write/Read Connectivity and Disable A1 and A0 determine which output is being programmed. D1 and D0 determine which input is connected to which output; D2 determines the enabled/disabled state of that output, with D2 = 1 (enable). When writing or reading, D3 is always 0. 0 1 A1 A0 D3 D2 D1 D0 Write/Read Output Current Level A1 and A0 determine which output is being programmed. D0 to D3 binarily program the output current level/voltage swing with the output current = 2 mA + (2 mA × decimal (D[3:0])). 1 0 0 0 0 D2 D1 D0 Broadcast Connectivity/Disable D1 and D0 determine which input is connected to all of the outputs. D2 determines the enabled/disabled state of all outputs with D2 = 1 (enable). When writing or reading, D3 is always 0. 1 0 0 1 D3 D2 D1 D0 Broadcast Output Current Level D0 to D3 binarily program the output current level/voltage swing with the output current = 2 mA + (2 mA × decimal (D[3:0])). The value is written to all outputs. Broadcast EQ Setting 1 0 1 1 D3 D2 D1 D0 Data inputs D0 to D3 set the input equalization level where: Gain(f ) = D[3:0]/15 × 40 log10(f/0.83 GHz). Program EQ Setting 1 1 A1 A0 D3 D2 D1 D0 A1 and A0 determine which input is being programmed. D0 to D3 set the input equalization level, where: Gain(f ) = D[3:0]⁄15 × 40 log10(f⁄0.83 GHz). |
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