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TSL2540 датащи(PDF) 24 Page - OSRAM GmbH |
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TSL2540 датащи(HTML) 24 Page - OSRAM GmbH |
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24 / 38 page ![]() Datasheet, Public Page 23 [v2-00] 2022-Dec-05 Document Feedback TSL2540 − Register Description CFG3 Register (Address 0xAB) Figure 34: CFG3 Register The SAI bit sets the device operational mode following the completion of an ALS cycle. If AINT and AIEN are both set or if PINT and PIEN are both set, causing an interrupt on the INT pin, and the SAI bit is set, then the oscillator will deactivate. The Device will appear as if PON = 0, however, PON will read as 1. The device can only be reactivated (oscillator enabled) by clearing the interrupts in the STATUS register. Addr: 0xAB CFG3 Bit Bit Name Default Access Bit Description 7 INT_READ_CLEAR 0 R/W If the Interrupt-Clear-by-Read bit is set, then all flag bits in the STATUS register will be reset whenever the STATUS register is read over I²C. 6:5 Reserved 10 R/W Reserved. 4SAI 0 R/W The Sleep After Interrupt bit is used to place the device into a low power mode upon an interrupt pin assertion. PON SAI INT Oscillator 0X X OFF 10 X ON 11 1 ON 11 0 OFF 3:0 Reserved 1100 R/W Reserved. |
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